.MODULE/RAM/BOOT=0/ABS=0 test;

{ SYSTEM I/O ADDRESS DEFINES }
.const  Sys_Ctrl_Reg= 		    0x3fff;
.const  Dm_Wait_Reg= 	            0x3ffe;
.const  Tperiod_Reg=                0x3ffd;
.const  Tcount_Reg=                 0x3ffc;
.const  Tscale_Reg=                 0x3ffb;
.const  Sport0_Rx_Words1=           0x3ffa;
.const  Sport0_Rx_Words0=           0x3ff9;
.const  Sport0_Tx_Words1=           0x3ff8;
.const  Sport0_Tx_Words0=           0x3ff7;
.const  Sport0_Ctrl_Reg=            0x3ff6;
.const  Sport0_Sclkdiv=             0x3ff5;
.const  Sport0_Rfsdiv=              0x3ff4;
.const  Sport0_Autobuf_Ctrl=        0x3ff3;
.const  Sport1_Ctrl_Reg=            0x3ff2;
.const  Sport1_Sclkdiv=             0x3ff1;
.const  Sport1_Rfsdiv=              0x3ff0;
.const  Sport1_Autobuf_Ctrl=        0x3fef;

.CONST comcrdy	= 0x0803;
.CONST comdrdy	= 0x0804;
.CONST cpudt 	= 0x0810;
.CONST dspdt	= 0x0811;

{ BOAD REGISTERS }
.CONST hs_readonly	= 0x0600;
.CONST handshake	= 0x0700;
.CONST dipswitch	= 0x0400;
.CONST codec_ctrl	= 0x0400;

{ CONTROLE BITS }
.CONST d2c	= 0x2000;
.CONST c2d	= 0x1000;
.CONST s8	= 0x8000;
.CONST s4	= 0x4000;
.CONST s2	= 0x2000;
.CONST s1	= 0x1000;
.CONST dc	= 0x1000;
.CONST c2denb	= 0x2000;
.CONST extenb	= 0x4000;

{ MEMORY STRUCTURE }
.CONST	dm_top		= 0x0800;
.CONST	dm_bottom	= 0x3BFF;
.CONST	pm_top		= 0x0000;
.CONST	pm_bottom	= 0x3FFF;

.CONST	ext_dm_top	= 0x0800;
.CONST	ext_dm_bottom	= 0x37FF;
.CONST	int_dm_top	= 0x3800;
.CONST	int_dm_bottom	= 0x3BFF;
.CONST	ext_pm_top	= 0x0800;
.CONST	ext_pm_bottom	= 0x3FFF;
.CONST	int_pm_top	= 0x0000;
.CONST	int_pm_bottom	= 0x07FF;

{ TERMINATE PROGRAM }
.CONST	end_of_prog	= 0x001D;

/******************** Special Macro Defines ********************/
#define data_to_mem(data,memory)	AX0=data; DM(memory)=AX0;
#define data_to_reg(data,register)	AX0=data; DM(register)=AX0;
#define interrupt_disable		IFC=0x3f; IMASK=0x00;
#define interrupt_s0_rx_enable		IFC=0x3f; IMASK=0x08;
#define interrupt_s0_tx_enable		IFC=0x3f; IMASK=0x10;
#define waiting_for_interrupt		idle;
#define direct_tx_port_0(i_reg,m_reg)	AX0=DM(i_reg,m_reg); TX0=AX0;
#define serial_port_0_disable		data_to_reg(0x0408,Sys_Ctrl_Reg)
#define serial_port_0_enable		data_to_reg(0x1408,Sys_Ctrl_Reg)
#define autobuf_port_0_disable		data_to_reg(0x0000,Sport0_Autobuf_Ctrl)
#define autobuf_port_0_enable		data_to_reg(0x0017,Sport0_Autobuf_Ctrl)
.MACRO codec_to_AR_reg_mono;
	SR0=DM(I3,M3); AY0=DM(I3,M3);
	SR=lshift SR0 by 8 (lo); AR=SR0 or AY0;
.ENDMACRO;
.MACRO SR0_reg_to_codec_mono;
	AY0=0xff; AR=SR0 and AY0; SR=lshift SR0 by -8 (lo);
	DM(I2,M2)=SR0; DM(I2,M2)=AR;
.ENDMACRO;

/******************** Buffer Memory Defines ********************/
.VAR/DM/RAM/ABS=0x0900/CIRC	fifo_tx[8];
.VAR/DM/RAM/ABS=0x0910/CIRC	fifo_rx[8];

/******************** Reset Vectors Defines ********************/
jump start;	nop; nop; nop;	{Reset Vector}
	RTI;	nop; nop; nop;	{irq2}
	RTI;	nop; nop; nop;	{sport0 TX}
	RTI;	nop; nop; nop;	{sport0 RX}
	RTI;	nop; nop; nop;	{irq0}
	RTI;	nop; nop; nop;	{irq1}
	RTI;	nop; nop; nop;	{timer}

/******************** Common Subroutines ********************/
codec_initialize:
	call codec_system_init;
	call codec_init_command_mode;
	call codec_init_data_mode;
	rts;
codec_system_init:
	data_to_reg(0x01,Dm_Wait_Reg)		/* 1 wait */
	data_to_reg(0xff,Sport0_Rfsdiv)		/* Multi-ch, 256bit */
	data_to_reg(0x00,Sport0_Sclkdiv)	/* divide rate */
	data_to_reg(0xff,Sport0_Tx_Words0)	/* LSB 16bit Tx */
	data_to_reg(0xff,Sport0_Rx_Words0)	/*           Rx */
	data_to_reg(0x00,Sport0_Tx_Words1)	/* MSB 16bit Tx */
	data_to_reg(0x00,Sport0_Rx_Words1)	/*           Rx */
	rts;
codec_init_command_mode:
	interrupt_disable
	serial_port_0_disable
	autobuf_port_0_disable
	data_to_mem(0x08,fifo_tx+0)	/* olb=1, clb=0(control) */
	data_to_mem(0x1c,fifo_tx+1)	/* 32KHz, Stereo, 16bit */
	data_to_mem(0x9a,fifo_tx+2)	/* 256bit, x1, gen.clk */
	data_to_mem(0x00,fifo_tx+3)	/* (reserved) */
	data_to_mem(0xc0,fifo_tx+4)	/* (reserved) */
	data_to_mem(0x00,fifo_tx+6)	/* (reserved) */
	I0=^fifo_tx; M0=1; L0=8; 
	I1=^fifo_rx; M1=1; L1=8; 
	data_to_reg(0xc707,Sport0_Ctrl_Reg)	/* CODEC --> Setting Mode */
	direct_tx_port_0(I0,M0)
	autobuf_port_0_enable			/* tx=I0, rx=I1 */
	serial_port_0_enable
	interrupt_s0_rx_enable
loop_1:
	waiting_for_interrupt
	call check_1;
	if ne jump loop_1;
	interrupt_s0_tx_enable
	data_to_mem(0x000C,fifo_tx+0)		/* clb set */
	waiting_for_interrupt
	waiting_for_interrupt
	waiting_for_interrupt
	rts;
check_1: 
	AX0=DM(fifo_rx+0); AY0=0x04; AR=AX0 and AY0;
	if ne jump chk_exit;
	AX0=DM(fifo_tx+1); AY0=DM(fifo_rx+1); AR=AX0-AY0;
	if ne jump chk_exit;
	AX0=DM(fifo_tx+2); AY0=DM(fifo_rx+2); AF=AX0 xor AY0;
	AX0=0xFF7F; AR=AX0 and AF;
chk_exit:
	rts;
codec_init_data_mode:
	interrupt_disable
	serial_port_0_disable
	autobuf_port_0_disable
	data_to_mem(0x00,fifo_tx+0)	/* (dummy) */
	data_to_mem(0x00,fifo_tx+1)	/*    |    */
	data_to_mem(0x00,fifo_tx+2)	/*    |    */
	data_to_mem(0x00,fifo_tx+3)	/* (dummy) */
	data_to_mem(0xc0,fifo_tx+4)	/* Output Enable, Lch : 0db ATT */
	data_to_mem(0x00,fifo_tx+5)	/*                Rch : 0db ATT */
	data_to_mem(0xc6,fifo_tx+6)	/* Input <- Line, Lch : gain 9dB */
	data_to_mem(0xf6,fifo_tx+7)	/*                Rch : gain 9dB */
	I0=^fifo_tx; M0=1; L0=8;
	I1=^fifo_rx; M1=1; L1=8;
	I2=^fifo_tx; M2=1; L2=2;		/* Data Buffer for Tx (L) */
	I3=^fifo_rx; M3=1; L3=2;		/*                 Rx (L) */
	data_to_reg(0x8607,Sport0_Ctrl_Reg)	/* CODEC --> Running Mode */
	data_to_reg(dc,codec_ctrl)		/* Change to Data Mode */
	direct_tx_port_0(I0,M0)
	autobuf_port_0_enable			/* tx=I0, rx=I1 */
	serial_port_0_enable
	interrupt_s0_rx_enable
	rts;

.VAR/DM/RAM/ABS=0x0800		interface;
				/* Offset : +0 = original wave data */
				/*        : +1 = effected wave data */
				/*        : +2 = delay offset for 2nd */
				/*        : +3 = delay offset for 3rd */
				/*        : +4 = delay offset for 4th */
				/*        : +5 = multiply data for 1st */
				/*        : +6 = multiply data for 2nd */
				/*        : +7 = multiply data for 3rd */
				/*        : +8 = multiply data for 4th */
.VAR/DM/RAM/ABS=0x2000/CIRC	data_fifo[4096];

start:
	call codec_initialize;		/* DSP_HEAD.H */
	I4=^data_fifo; M4=1; L4=4096;
	I5=^data_fifo; M5=1; L5=0;
main:
	codec_to_AR_reg_mono;		/* Get A/D Data : DSP_HEAD.H */
	DM(I4,M4)=AR;
	DM(interface+0)=AR;
	AY0=I4;
	AY1=0x2fff;
	MY0=DM(interface+5);
	MR=AR*MY0 (ss);
	AX0=DM(interface+2);
	AR=AX0+AY0;
	AR=AR and AY1;
	I5=AR;
	AR=DM(I5,M5);
	MY0=DM(interface+6);
	MR=MR+AR*MY0 (ss);
	AX0=DM(interface+3);
	AR=AX0+AY0;
	AR=AR and AY1;
	I5=AR;
	AR=DM(I5,M5);
	MY0=DM(interface+7);
	MR=MR+AR*MY0 (ss);
	AX0=DM(interface+4);
	AR=AX0+AY0;
	AR=AR and AY1;
	I5=AR;
	AR=DM(I5,M5);
	MY0=DM(interface+8);
	MR=MR+AR*MY0 (ss);
	SR0=MR1;
	DM(interface+1)=SR0;
	SR0_reg_to_codec_mono;		/* Put to D/A : DSP_HEAD.H */
	waiting_for_interrupt
	jump main;

.ENDMOD;

=============================================================================


.MODULE/RAM/BOOT = 0/ABS = 0	transfer;

.const  Sys_Ctrl_Reg= 		    0x3fff;
.const  Dm_Wait_Reg= 	            0x3ffe;
.const  Tperiod_Reg=                0x3ffd;
.const  Tcount_Reg=                 0x3ffc;
.const  Tscale_Reg=                 0x3ffb;
.const  Sport0_Rx_Words1=           0x3ffa;
.const  Sport0_Rx_Words0=           0x3ff9;
.const  Sport0_Tx_Words1=           0x3ff8;
.const  Sport0_Tx_Words0=           0x3ff7;
.const  Sport0_Ctrl_Reg=            0x3ff6;
.const  Sport0_Sclkdiv=             0x3ff5;
.const  Sport0_Rfsdiv=              0x3ff4;
.const  Sport0_Autobuf_Ctrl=        0x3ff3;
.const  Sport1_Ctrl_Reg=            0x3ff2;
.const  Sport1_Sclkdiv=             0x3ff1;
.const  Sport1_Rfsdiv=              0x3ff0;
.const  Sport1_Autobuf_Ctrl=        0x3fef;

{ SYSTEM I/O ADDRESS DEFINES }
.const  Sys_Ctrl_Reg= 		    0x3fff;
.const  Dm_Wait_Reg= 	            0x3ffe;
.const  Tperiod_Reg=                0x3ffd;
.const  Tcount_Reg=                 0x3ffc;
.const  Tscale_Reg=                 0x3ffb;
.const  Sport0_Rx_Words1=           0x3ffa;
.const  Sport0_Rx_Words0=           0x3ff9;
.const  Sport0_Tx_Words1=           0x3ff8;
.const  Sport0_Tx_Words0=           0x3ff7;
.const  Sport0_Ctrl_Reg=            0x3ff6;
.const  Sport0_Sclkdiv=             0x3ff5;
.const  Sport0_Rfsdiv=              0x3ff4;
.const  Sport0_Autobuf_Ctrl=        0x3ff3;
.const  Sport1_Ctrl_Reg=            0x3ff2;
.const  Sport1_Sclkdiv=             0x3ff1;
.const  Sport1_Rfsdiv=              0x3ff0;
.const  Sport1_Autobuf_Ctrl=        0x3fef;

.CONST comcrdy	= 0x0803;
.CONST comdrdy	= 0x0804;
.CONST cpudt 	= 0x0810;
.CONST dspdt	= 0x0811;

{ BOAD REGISTERS }
.CONST hs_readonly	= 0x0600;
.CONST handshake	= 0x0700;
.CONST dipswitch	= 0x0400;
.CONST codec_ctrl	= 0x0400;

{ CONTROLE BITS }
.CONST d2c	= 0x2000;
.CONST c2d	= 0x1000;
.CONST s8	= 0x8000;
.CONST s4	= 0x4000;
.CONST s2	= 0x2000;
.CONST s1	= 0x1000;
.CONST dc	= 0x1000;
.CONST c2denb	= 0x2000;
.CONST extenb	= 0x4000;

{ MEMORY STRUCTURE }
.CONST	dm_top		= 0x0800;
.CONST	dm_bottom	= 0x3BFF;
.CONST	pm_top		= 0x0000;
.CONST	pm_bottom	= 0x3FFF;

.CONST	ext_dm_top	= 0x0800;
.CONST	ext_dm_bottom	= 0x37FF;
.CONST	int_dm_top	= 0x3800;
.CONST	int_dm_bottom	= 0x3BFF;
.CONST	ext_pm_top	= 0x0800;
.CONST	ext_pm_bottom	= 0x3FFF;
.CONST	int_pm_top	= 0x0000;
.CONST	int_pm_bottom	= 0x07FF;

{ TERMINATE PROGRAM }
.CONST	end_of_prog	= 0x001D;

/******************** Special Macro Defines ********************/
#define data_to_mem(data,memory)	AX0=data; DM(memory)=AX0;
#define data_to_reg(data,register)	AX0=data; DM(register)=AX0;
#define interrupt_disable		IFC=0x3f; IMASK=0x00;
#define interrupt_s0_rx_enable		IFC=0x3f; IMASK=0x08;
#define interrupt_s0_tx_enable		IFC=0x3f; IMASK=0x10;
#define waiting_for_interrupt		idle;
#define direct_tx_port_0(i_reg,m_reg)	AX0=DM(i_reg,m_reg); TX0=AX0;
#define serial_port_0_disable		data_to_reg(0x0408,Sys_Ctrl_Reg)
#define serial_port_0_enable		data_to_reg(0x1408,Sys_Ctrl_Reg)
#define autobuf_port_0_disable		data_to_reg(0x0000,Sport0_Autobuf_Ctrl)
#define autobuf_port_0_enable		data_to_reg(0x0017,Sport0_Autobuf_Ctrl)
.MACRO codec_to_AR_reg_mono;
	SR0=DM(I3,M3); AY0=DM(I3,M3);
	SR=lshift SR0 by 8 (lo); AR=SR0 or AY0;
.ENDMACRO;
.MACRO SR0_reg_to_codec_mono;
	AY0=0xff; AR=SR0 and AY0; SR=lshift SR0 by -8 (lo);
	DM(I2,M2)=SR0; DM(I2,M2)=AR;
.ENDMACRO;

/******************** Buffer Memory Defines ********************/
.VAR/DM/RAM/ABS=0x0900/CIRC	fifo_tx[8];
.VAR/DM/RAM/ABS=0x0910/CIRC	fifo_rx[8];

/******************** Reset Vectors Defines ********************/
jump start;	nop; nop; nop;	{Reset Vector}
	RTI;	nop; nop; nop;	{irq2}
	RTI;	nop; nop; nop;	{sport0 TX}
	RTI;	nop; nop; nop;	{sport0 RX}
	RTI;	nop; nop; nop;	{irq0}
	RTI;	nop; nop; nop;	{irq1}
	RTI;	nop; nop; nop;	{timer}

/******************** Common Subroutines ********************/
codec_initialize:
	call codec_system_init;
	call codec_init_command_mode;
	call codec_init_data_mode;
	rts;
codec_system_init:
	data_to_reg(0x01,Dm_Wait_Reg)		/* 1 wait */
	data_to_reg(0xff,Sport0_Rfsdiv)		/* Multi-ch, 256bit */
	data_to_reg(0x00,Sport0_Sclkdiv)	/* divide rate */
	data_to_reg(0xff,Sport0_Tx_Words0)	/* LSB 16bit Tx */
	data_to_reg(0xff,Sport0_Rx_Words0)	/*           Rx */
	data_to_reg(0x00,Sport0_Tx_Words1)	/* MSB 16bit Tx */
	data_to_reg(0x00,Sport0_Rx_Words1)	/*           Rx */
	rts;
codec_init_command_mode:
	interrupt_disable
	serial_port_0_disable
	autobuf_port_0_disable
	data_to_mem(0x08,fifo_tx+0)	/* olb=1, clb=0(control) */
	data_to_mem(0x1c,fifo_tx+1)	/* 32KHz, Stereo, 16bit */
	data_to_mem(0x9a,fifo_tx+2)	/* 256bit, x1, gen.clk */
	data_to_mem(0x00,fifo_tx+3)	/* (reserved) */
	data_to_mem(0xc0,fifo_tx+4)	/* (reserved) */
	data_to_mem(0x00,fifo_tx+6)	/* (reserved) */
	I0=^fifo_tx; M0=1; L0=8; 
	I1=^fifo_rx; M1=1; L1=8; 
	data_to_reg(0xc707,Sport0_Ctrl_Reg)	/* CODEC --> Setting Mode */
	direct_tx_port_0(I0,M0)
	autobuf_port_0_enable			/* tx=I0, rx=I1 */
	serial_port_0_enable
	interrupt_s0_rx_enable
loop_1:
	waiting_for_interrupt
	call check_1;
	if ne jump loop_1;
	interrupt_s0_tx_enable
	data_to_mem(0x000C,fifo_tx+0)		/* clb set */
	waiting_for_interrupt
	waiting_for_interrupt
	waiting_for_interrupt
	rts;
check_1: 
	AX0=DM(fifo_rx+0); AY0=0x04; AR=AX0 and AY0;
	if ne jump chk_exit;
	AX0=DM(fifo_tx+1); AY0=DM(fifo_rx+1); AR=AX0-AY0;
	if ne jump chk_exit;
	AX0=DM(fifo_tx+2); AY0=DM(fifo_rx+2); AF=AX0 xor AY0;
	AX0=0xFF7F; AR=AX0 and AF;
chk_exit:
	rts;
codec_init_data_mode:
	interrupt_disable
	serial_port_0_disable
	autobuf_port_0_disable
	data_to_mem(0x00,fifo_tx+0)	/* (dummy) */
	data_to_mem(0x00,fifo_tx+1)	/*    |    */
	data_to_mem(0x00,fifo_tx+2)	/*    |    */
	data_to_mem(0x00,fifo_tx+3)	/* (dummy) */
	data_to_mem(0xc0,fifo_tx+4)	/* Output Enable, Lch : 0db ATT */
	data_to_mem(0x00,fifo_tx+5)	/*                Rch : 0db ATT */
	data_to_mem(0xc6,fifo_tx+6)	/* Input <- Line, Lch : gain 9dB */
	data_to_mem(0xf6,fifo_tx+7)	/*                Rch : gain 9dB */
	I0=^fifo_tx; M0=1; L0=8;
	I1=^fifo_rx; M1=1; L1=8;
	I2=^fifo_tx; M2=1; L2=2;		/* Data Buffer for Tx (L) */
	I3=^fifo_rx; M3=1; L3=2;		/*                 Rx (L) */
	data_to_reg(0x8607,Sport0_Ctrl_Reg)	/* CODEC --> Running Mode */
	data_to_reg(dc,codec_ctrl)		/* Change to Data Mode */
	direct_tx_port_0(I0,M0)
	autobuf_port_0_enable			/* tx=I0, rx=I1 */
	serial_port_0_enable
	interrupt_s0_rx_enable
	rts;

{ interupt vector table }
        jump start; RTI; RTI; RTI;      {Reset Vector}    
	RTI; RTI; RTI; RTI;		{irq2}
        RTI; RTI; RTI; RTI;             {sport0 TX}
        RTI; RTI; RTI; RTI;             {sport0 RX}
        RTI; RTI; RTI; RTI;             {irq0}
        RTI; RTI; RTI; RTI;             {irq1}
        RTI; RTI; RTI; RTI;             {timer}

#include <dsp_tail.h>;

start:
	AX0 = 0x0408; DM(Sys_Ctrl_Reg) = AX0;
	AX0 = 1; DM(Dm_Wait_Reg)  = AX0;
	
	AX0 = 0; DM(comdrdy) = AX0; DM(comcrdy) = AX0;
	AX0 = d2c; DM(handshake) = AX0;

testtop:
	CALL get_wd;

	AY0 = SI;
	AR = AY0 + 1;
	SI = AR;

	CALL put_wd;

	JUMP testtop;

.ENDMOD;

=============================================================================


.MODULE/RAM/BOOT = 0/ABS = 0	test;

.const  Sys_Ctrl_Reg= 		    0x3fff;
.const  Dm_Wait_Reg= 	            0x3ffe;
.const  Tperiod_Reg=                0x3ffd;
.const  Tcount_Reg=                 0x3ffc;
.const  Tscale_Reg=                 0x3ffb;
.const  Sport0_Rx_Words1=           0x3ffa;
.const  Sport0_Rx_Words0=           0x3ff9;
.const  Sport0_Tx_Words1=           0x3ff8;
.const  Sport0_Tx_Words0=           0x3ff7;
.const  Sport0_Ctrl_Reg=            0x3ff6;
.const  Sport0_Sclkdiv=             0x3ff5;
.const  Sport0_Rfsdiv=              0x3ff4;
.const  Sport0_Autobuf_Ctrl=        0x3ff3;
.const  Sport1_Ctrl_Reg=            0x3ff2;
.const  Sport1_Sclkdiv=             0x3ff1;
.const  Sport1_Rfsdiv=              0x3ff0;
.const  Sport1_Autobuf_Ctrl=        0x3fef;

{ SYSTEM I/O ADDRESS DEFINES }
.const  Sys_Ctrl_Reg= 		    0x3fff;
.const  Dm_Wait_Reg= 	            0x3ffe;
.const  Tperiod_Reg=                0x3ffd;
.const  Tcount_Reg=                 0x3ffc;
.const  Tscale_Reg=                 0x3ffb;
.const  Sport0_Rx_Words1=           0x3ffa;
.const  Sport0_Rx_Words0=           0x3ff9;
.const  Sport0_Tx_Words1=           0x3ff8;
.const  Sport0_Tx_Words0=           0x3ff7;
.const  Sport0_Ctrl_Reg=            0x3ff6;
.const  Sport0_Sclkdiv=             0x3ff5;
.const  Sport0_Rfsdiv=              0x3ff4;
.const  Sport0_Autobuf_Ctrl=        0x3ff3;
.const  Sport1_Ctrl_Reg=            0x3ff2;
.const  Sport1_Sclkdiv=             0x3ff1;
.const  Sport1_Rfsdiv=              0x3ff0;
.const  Sport1_Autobuf_Ctrl=        0x3fef;

.CONST comcrdy	= 0x0803;
.CONST comdrdy	= 0x0804;
.CONST cpudt 	= 0x0810;
.CONST dspdt	= 0x0811;

{ BOAD REGISTERS }
.CONST hs_readonly	= 0x0600;
.CONST handshake	= 0x0700;
.CONST dipswitch	= 0x0400;
.CONST codec_ctrl	= 0x0400;

{ CONTROLE BITS }
.CONST d2c	= 0x2000;
.CONST c2d	= 0x1000;
.CONST s8	= 0x8000;
.CONST s4	= 0x4000;
.CONST s2	= 0x2000;
.CONST s1	= 0x1000;
.CONST dc	= 0x1000;
.CONST c2denb	= 0x2000;
.CONST extenb	= 0x4000;

{ MEMORY STRUCTURE }
.CONST	dm_top		= 0x0800;
.CONST	dm_bottom	= 0x3BFF;
.CONST	pm_top		= 0x0000;
.CONST	pm_bottom	= 0x3FFF;

.CONST	ext_dm_top	= 0x0800;
.CONST	ext_dm_bottom	= 0x37FF;
.CONST	int_dm_top	= 0x3800;
.CONST	int_dm_bottom	= 0x3BFF;
.CONST	ext_pm_top	= 0x0800;
.CONST	ext_pm_bottom	= 0x3FFF;
.CONST	int_pm_top	= 0x0000;
.CONST	int_pm_bottom	= 0x07FF;

{ TERMINATE PROGRAM }
.CONST	end_of_prog	= 0x001D;

/******************** Special Macro Defines ********************/
#define data_to_mem(data,memory)	AX0=data; DM(memory)=AX0;
#define data_to_reg(data,register)	AX0=data; DM(register)=AX0;
#define interrupt_disable		IFC=0x3f; IMASK=0x00;
#define interrupt_s0_rx_enable		IFC=0x3f; IMASK=0x08;
#define interrupt_s0_tx_enable		IFC=0x3f; IMASK=0x10;
#define waiting_for_interrupt		idle;
#define direct_tx_port_0(i_reg,m_reg)	AX0=DM(i_reg,m_reg); TX0=AX0;
#define serial_port_0_disable		data_to_reg(0x0408,Sys_Ctrl_Reg)
#define serial_port_0_enable		data_to_reg(0x1408,Sys_Ctrl_Reg)
#define autobuf_port_0_disable		data_to_reg(0x0000,Sport0_Autobuf_Ctrl)
#define autobuf_port_0_enable		data_to_reg(0x0017,Sport0_Autobuf_Ctrl)
.MACRO codec_to_AR_reg_mono;
	SR0=DM(I3,M3); AY0=DM(I3,M3);
	SR=lshift SR0 by 8 (lo); AR=SR0 or AY0;
.ENDMACRO;
.MACRO SR0_reg_to_codec_mono;
	AY0=0xff; AR=SR0 and AY0; SR=lshift SR0 by -8 (lo);
	DM(I2,M2)=SR0; DM(I2,M2)=AR;
.ENDMACRO;

/******************** Buffer Memory Defines ********************/
.VAR/DM/RAM/ABS=0x0900/CIRC	fifo_tx[8];
.VAR/DM/RAM/ABS=0x0910/CIRC	fifo_rx[8];

/******************** Reset Vectors Defines ********************/
jump start;	nop; nop; nop;	{Reset Vector}
	RTI;	nop; nop; nop;	{irq2}
	RTI;	nop; nop; nop;	{sport0 TX}
	RTI;	nop; nop; nop;	{sport0 RX}
	RTI;	nop; nop; nop;	{irq0}
	RTI;	nop; nop; nop;	{irq1}
	RTI;	nop; nop; nop;	{timer}

/******************** Common Subroutines ********************/
codec_initialize:
	call codec_system_init;
	call codec_init_command_mode;
	call codec_init_data_mode;
	rts;
codec_system_init:
	data_to_reg(0x01,Dm_Wait_Reg)		/* 1 wait */
	data_to_reg(0xff,Sport0_Rfsdiv)		/* Multi-ch, 256bit */
	data_to_reg(0x00,Sport0_Sclkdiv)	/* divide rate */
	data_to_reg(0xff,Sport0_Tx_Words0)	/* LSB 16bit Tx */
	data_to_reg(0xff,Sport0_Rx_Words0)	/*           Rx */
	data_to_reg(0x00,Sport0_Tx_Words1)	/* MSB 16bit Tx */
	data_to_reg(0x00,Sport0_Rx_Words1)	/*           Rx */
	rts;
codec_init_command_mode:
	interrupt_disable
	serial_port_0_disable
	autobuf_port_0_disable
	data_to_mem(0x08,fifo_tx+0)	/* olb=1, clb=0(control) */
	data_to_mem(0x1c,fifo_tx+1)	/* 32KHz, Stereo, 16bit */
	data_to_mem(0x9a,fifo_tx+2)	/* 256bit, x1, gen.clk */
	data_to_mem(0x00,fifo_tx+3)	/* (reserved) */
	data_to_mem(0xc0,fifo_tx+4)	/* (reserved) */
	data_to_mem(0x00,fifo_tx+6)	/* (reserved) */
	I0=^fifo_tx; M0=1; L0=8; 
	I1=^fifo_rx; M1=1; L1=8; 
	data_to_reg(0xc707,Sport0_Ctrl_Reg)	/* CODEC --> Setting Mode */
	direct_tx_port_0(I0,M0)
	autobuf_port_0_enable			/* tx=I0, rx=I1 */
	serial_port_0_enable
	interrupt_s0_rx_enable
loop_1:
	waiting_for_interrupt
	call check_1;
	if ne jump loop_1;
	interrupt_s0_tx_enable
	data_to_mem(0x000C,fifo_tx+0)		/* clb set */
	waiting_for_interrupt
	waiting_for_interrupt
	waiting_for_interrupt
	rts;
check_1: 
	AX0=DM(fifo_rx+0); AY0=0x04; AR=AX0 and AY0;
	if ne jump chk_exit;
	AX0=DM(fifo_tx+1); AY0=DM(fifo_rx+1); AR=AX0-AY0;
	if ne jump chk_exit;
	AX0=DM(fifo_tx+2); AY0=DM(fifo_rx+2); AF=AX0 xor AY0;
	AX0=0xFF7F; AR=AX0 and AF;
chk_exit:
	rts;
codec_init_data_mode:
	interrupt_disable
	serial_port_0_disable
	autobuf_port_0_disable
	data_to_mem(0x00,fifo_tx+0)	/* (dummy) */
	data_to_mem(0x00,fifo_tx+1)	/*    |    */
	data_to_mem(0x00,fifo_tx+2)	/*    |    */
	data_to_mem(0x00,fifo_tx+3)	/* (dummy) */
	data_to_mem(0xc0,fifo_tx+4)	/* Output Enable, Lch : 0db ATT */
	data_to_mem(0x00,fifo_tx+5)	/*                Rch : 0db ATT */
	data_to_mem(0xc6,fifo_tx+6)	/* Input <- Line, Lch : gain 9dB */
	data_to_mem(0xf6,fifo_tx+7)	/*                Rch : gain 9dB */
	I0=^fifo_tx; M0=1; L0=8;
	I1=^fifo_rx; M1=1; L1=8;
	I2=^fifo_tx; M2=1; L2=2;		/* Data Buffer for Tx (L) */
	I3=^fifo_rx; M3=1; L3=2;		/*                 Rx (L) */
	data_to_reg(0x8607,Sport0_Ctrl_Reg)	/* CODEC --> Running Mode */
	data_to_reg(dc,codec_ctrl)		/* Change to Data Mode */
	direct_tx_port_0(I0,M0)
	autobuf_port_0_enable			/* tx=I0, rx=I1 */
	serial_port_0_enable
	interrupt_s0_rx_enable
	rts;

.VAR/DM/RAM/ABS=0x2010/CIRC	s0_ctl_send[8]; /* 2010-2017 */
.VAR/DM/RAM/ABS=0x2020/CIRC	s0_ctl_recv[8]; /* 2020-2027 */
.VAR/DM/RAM/ABS=0x2030/CIRC	s0_dat_send[8]; /* 2030-2037 */
.VAR/DM/RAM/ABS=0x2040/CIRC	s0_dat_recv[8]; /* 2040-2047 */

#define	ts1	0
#define	ts2	1
#define	ts3	2
#define	ts4	3
#define	ts5	4
#define	ts6	5
#define	ts7	6
#define	ts8	7

{ interupt vector table }
        jump start; RTI; RTI; RTI;	{Reset Vector}    
	RTI; RTI; RTI; RTI;		{irq2}
        jump s0send; RTI; RTI; RTI;	{sport0 TX}
        jump s0recv; RTI; RTI; RTI;	{sport0 RX}
        RTI; RTI; RTI; RTI;		{irq0}
        RTI; RTI; RTI; RTI;		{irq1}
        RTI; RTI; RTI; RTI;		{timer}

#include <dsp_tail.h>;

start:
	ifc=0x3f; IMASK=0x00;			/* int disable */
	AX0 = 0x0408; DM(Sys_Ctrl_Reg) = AX0;	/* sport0 disable */
	AX0 = 1; DM(Dm_Wait_Reg)  = AX0;
	
initcodec:
	AX0=0x00ff; DM(Sport0_Tx_Words0)=AX0;	/* 64bit */ 
	AX0=0x00ff; DM(Sport0_Rx_Words0)=AX0;	/* 64bit */
	AX0=0x0000; DM(Sport0_Tx_Words1)=AX0;
	AX0=0x0000; DM(Sport0_Rx_Words1)=AX0;
	AX0=0xc707; DM(Sport0_Ctrl_Reg)=AX0;	/* rfs send mode */
	AX0=0x0000; DM(Sport0_Sclkdiv)=AX0;
	AX0=255;   DM(Sport0_Rfsdiv)=AX0;	/* multichannel,256bit */
{ control mode timeslot }
	AX0=0x8;	DM(s0_ctl_send+ts1)=AX0; /* olb=1,clb=0 */
/*	AX0=0x0;	DM(s0_ctl_send+ts1)=AX0;    olb=0,clb=0 */
	AX0=0x34;	DM(s0_ctl_send+ts2)=AX0; /* 48KHz,st,16bit */
	AX0=0x9a;	DM(s0_ctl_send+ts3)=AX0; /* 256b,x1,gen.clk */
	AX0=0;		DM(s0_ctl_send+ts4)=AX0;
	AX0=0xc0;	DM(s0_ctl_send+ts5)=AX0;
	AX0=0;		DM(s0_ctl_send+ts6)=AX0;
	AX0=0;		DM(s0_ctl_send+ts7)=AX0;
	AX0=0;		DM(s0_ctl_send+ts8)=AX0;
	AX0=0xffff;	DM(s0_ctl_recv+ts1)=AX0;
	AX0=0xffff;	DM(s0_ctl_recv+ts2)=AX0;
	AX0=0xffff;	DM(s0_ctl_recv+ts3)=AX0;
{ data time slot }	
	AX0=0x0;	DM(s0_dat_send+ts1)=AX0;
	AX0=0x0;	DM(s0_dat_send+ts2)=AX0;
	AX0=0x0;	DM(s0_dat_send+ts3)=AX0;
	AX0=0x0;	DM(s0_dat_send+ts4)=AX0;
	AX0=0xc2;	DM(s0_dat_send+ts5)=AX0; /* out enb,Rch:3dbATT */
	AX0=0x02;	DM(s0_dat_send+ts6)=AX0; /* Rch:3dbATT */
	AX0=0xdc;	DM(s0_dat_send+ts7)=AX0; /* AUX-I,Lch:gain24dB */
	AX0=0xfc;	DM(s0_dat_send+ts8)=AX0; /* AUX-I,Rch:gain24dB */
	AX0=0xaa;	DM(s0_dat_recv+ts1)=AX0;
	AX0=0xaa;	DM(s0_dat_recv+ts2)=AX0;
	AX0=0xaa;	DM(s0_dat_recv+ts3)=AX0;
	AX0=0x0;	DM(s0_dat_recv+ts4)=AX0;
	AX0=0x0;	DM(s0_dat_recv+ts5)=AX0;
	AX0=0x0;	DM(s0_dat_recv+ts6)=AX0;
	AX0=0x0;	DM(s0_dat_recv+ts7)=AX0;
	AX0=0x0;	DM(s0_dat_recv+ts8)=AX0;
{ control mode set }
	I0 =^s0_ctl_send; M0=1; L0=8; 
	I1 =^s0_ctl_recv; M1=1; L1=8; 
	AX0 =DM(I0,M0); TX0=AX0;
	AX0=0x17; 		/* tx=I0,rx=I1 autobuf enable */
	DM(Sport0_Autobuf_Ctrl)=AX0;
	AX0 = 0x1408; DM(Sys_Ctrl_Reg) = AX0;	/* sport0 enable */
	ifc=0x3f; 				/* all int clr */
	IMASK=0x08;				/* s0 rx int enable */
loop1:	idle;
	CALL control_mode_chk;
	IF NE jump loop1;
	ifc=0x3f; 
	IMASK=0x10;				/* s0 tx int enb */
	AX0=0x0C; DM(s0_ctl_send+ts1)=AX0;	/* clb set */
/*	AX0=0x04; DM(s0_ctl_send+ts1)=AX0;	   clb set */
	idle;
	idle;
	idle;
	IMASK=0; IFC=0x3F; 			
	AX0=0x00; DM(Sport0_Autobuf_Ctrl)=AX0;
	AX0 = 0x0408; DM(Sys_Ctrl_Reg) = AX0;	/* sport0 disable */
{ dsp set data mode }	
	AX0=0x8607; DM(Sport0_Ctrl_Reg)=AX0;	/* rfs receive mode */
	AX0=0xff;   DM(Sport0_Tx_Words0)=AX0;   /* 64bit */
	AX0=0xff;   DM(Sport0_Rx_Words0)=AX0;	/* 64bit */
	AX0=0x00;   DM(Sport0_Tx_Words1)=AX0;
	AX0=0x00;   DM(Sport0_Rx_Words1)=AX0;
	I0 =^s0_dat_send; M0=1; L0=8;
	I1 =^s0_dat_recv; M1=1; L1=8;
	I2 =^s0_dat_recv; M2=1; L2=4;
	I3 =^s0_dat_send; M3=1; L3=4;
	AX0 = 0x1408; DM(Sys_Ctrl_Reg) = AX0; /* sport0 enable */
	AX0=DM(I0,M0); TX0=AX0;		
	AX0=0x17; 		/* tx=I0,rx=I1 autobuf enable */
	DM(Sport0_Autobuf_Ctrl)=AX0;   
	AX0=dc;	DM(codec_ctrl)=AX0;	/* set dc to high */
	IFC=0x3f; IMASK=0x08;	
loop2:	idle;
	AY1=DM(I2,M2); DM(I3,M3)=AY1;	/* left  msb 8bit */
	AY1=DM(I2,M2); DM(I3,M3)=AY1;	/* left  lsb 8bit */
	AY1=DM(I2,M2); DM(I3,M3)=AY1;	/* right msb 8bit */
	AY1=DM(I2,M2); DM(I3,M3)=AY1;	/* right msb 8bit */
	jump loop2;
	
control_mode_chk: 
	{ for CS4215 rev.1 }
	AX0=DM(s0_ctl_recv+ts1);
	AY0=0x04; AR=AX0 and AY0;
	IF NE jump chk1;
	AX0=DM(s0_ctl_send+ts2);
	AY0=DM(s0_ctl_recv+ts2);
	AR=AX0-AY0;
	IF NE jump chk1;
	AX0=DM(s0_ctl_send+ts3);
	AY0=DM(s0_ctl_recv+ts3);
	AF=AX0 xor AY0;
	AX0=0xFF7F; AR=AX0 and AF;
chk1:	rts;

s0send:	rti;
s0recv:	rti;

.ENDMOD;

=============================================================================


.MODULE/RAM/BOOT = 0/ABS = 0	sine;

.const  Sys_Ctrl_Reg= 		    0x3fff;
.const  Dm_Wait_Reg= 	            0x3ffe;
.const  Tperiod_Reg=                0x3ffd;
.const  Tcount_Reg=                 0x3ffc;
.const  Tscale_Reg=                 0x3ffb;
.const  Sport0_Rx_Words1=           0x3ffa;
.const  Sport0_Rx_Words0=           0x3ff9;
.const  Sport0_Tx_Words1=           0x3ff8;
.const  Sport0_Tx_Words0=           0x3ff7;
.const  Sport0_Ctrl_Reg=            0x3ff6;
.const  Sport0_Sclkdiv=             0x3ff5;
.const  Sport0_Rfsdiv=              0x3ff4;
.const  Sport0_Autobuf_Ctrl=        0x3ff3;
.const  Sport1_Ctrl_Reg=            0x3ff2;
.const  Sport1_Sclkdiv=             0x3ff1;
.const  Sport1_Rfsdiv=              0x3ff0;
.const  Sport1_Autobuf_Ctrl=        0x3fef;

{ SYSTEM I/O ADDRESS DEFINES }
.const  Sys_Ctrl_Reg= 		    0x3fff;
.const  Dm_Wait_Reg= 	            0x3ffe;
.const  Tperiod_Reg=                0x3ffd;
.const  Tcount_Reg=                 0x3ffc;
.const  Tscale_Reg=                 0x3ffb;
.const  Sport0_Rx_Words1=           0x3ffa;
.const  Sport0_Rx_Words0=           0x3ff9;
.const  Sport0_Tx_Words1=           0x3ff8;
.const  Sport0_Tx_Words0=           0x3ff7;
.const  Sport0_Ctrl_Reg=            0x3ff6;
.const  Sport0_Sclkdiv=             0x3ff5;
.const  Sport0_Rfsdiv=              0x3ff4;
.const  Sport0_Autobuf_Ctrl=        0x3ff3;
.const  Sport1_Ctrl_Reg=            0x3ff2;
.const  Sport1_Sclkdiv=             0x3ff1;
.const  Sport1_Rfsdiv=              0x3ff0;
.const  Sport1_Autobuf_Ctrl=        0x3fef;

.CONST comcrdy	= 0x0803;
.CONST comdrdy	= 0x0804;
.CONST cpudt 	= 0x0810;
.CONST dspdt	= 0x0811;

{ BOAD REGISTERS }
.CONST hs_readonly	= 0x0600;
.CONST handshake	= 0x0700;
.CONST dipswitch	= 0x0400;
.CONST codec_ctrl	= 0x0400;

{ CONTROLE BITS }
.CONST d2c	= 0x2000;
.CONST c2d	= 0x1000;
.CONST s8	= 0x8000;
.CONST s4	= 0x4000;
.CONST s2	= 0x2000;
.CONST s1	= 0x1000;
.CONST dc	= 0x1000;
.CONST c2denb	= 0x2000;
.CONST extenb	= 0x4000;

{ MEMORY STRUCTURE }
.CONST	dm_top		= 0x0800;
.CONST	dm_bottom	= 0x3BFF;
.CONST	pm_top		= 0x0000;
.CONST	pm_bottom	= 0x3FFF;

.CONST	ext_dm_top	= 0x0800;
.CONST	ext_dm_bottom	= 0x37FF;
.CONST	int_dm_top	= 0x3800;
.CONST	int_dm_bottom	= 0x3BFF;
.CONST	ext_pm_top	= 0x0800;
.CONST	ext_pm_bottom	= 0x3FFF;
.CONST	int_pm_top	= 0x0000;
.CONST	int_pm_bottom	= 0x07FF;

{ TERMINATE PROGRAM }
.CONST	end_of_prog	= 0x001D;

/******************** Special Macro Defines ********************/
#define data_to_mem(data,memory)	AX0=data; DM(memory)=AX0;
#define data_to_reg(data,register)	AX0=data; DM(register)=AX0;
#define interrupt_disable		IFC=0x3f; IMASK=0x00;
#define interrupt_s0_rx_enable		IFC=0x3f; IMASK=0x08;
#define interrupt_s0_tx_enable		IFC=0x3f; IMASK=0x10;
#define waiting_for_interrupt		idle;
#define direct_tx_port_0(i_reg,m_reg)	AX0=DM(i_reg,m_reg); TX0=AX0;
#define serial_port_0_disable		data_to_reg(0x0408,Sys_Ctrl_Reg)
#define serial_port_0_enable		data_to_reg(0x1408,Sys_Ctrl_Reg)
#define autobuf_port_0_disable		data_to_reg(0x0000,Sport0_Autobuf_Ctrl)
#define autobuf_port_0_enable		data_to_reg(0x0017,Sport0_Autobuf_Ctrl)
.MACRO codec_to_AR_reg_mono;
	SR0=DM(I3,M3); AY0=DM(I3,M3);
	SR=lshift SR0 by 8 (lo); AR=SR0 or AY0;
.ENDMACRO;
.MACRO SR0_reg_to_codec_mono;
	AY0=0xff; AR=SR0 and AY0; SR=lshift SR0 by -8 (lo);
	DM(I2,M2)=SR0; DM(I2,M2)=AR;
.ENDMACRO;

/******************** Buffer Memory Defines ********************/
.VAR/DM/RAM/ABS=0x0900/CIRC	fifo_tx[8];
.VAR/DM/RAM/ABS=0x0910/CIRC	fifo_rx[8];

/******************** Reset Vectors Defines ********************/
jump start;	nop; nop; nop;	{Reset Vector}
	RTI;	nop; nop; nop;	{irq2}
	RTI;	nop; nop; nop;	{sport0 TX}
	RTI;	nop; nop; nop;	{sport0 RX}
	RTI;	nop; nop; nop;	{irq0}
	RTI;	nop; nop; nop;	{irq1}
	RTI;	nop; nop; nop;	{timer}

/******************** Common Subroutines ********************/
codec_initialize:
	call codec_system_init;
	call codec_init_command_mode;
	call codec_init_data_mode;
	rts;
codec_system_init:
	data_to_reg(0x01,Dm_Wait_Reg)		/* 1 wait */
	data_to_reg(0xff,Sport0_Rfsdiv)		/* Multi-ch, 256bit */
	data_to_reg(0x00,Sport0_Sclkdiv)	/* divide rate */
	data_to_reg(0xff,Sport0_Tx_Words0)	/* LSB 16bit Tx */
	data_to_reg(0xff,Sport0_Rx_Words0)	/*           Rx */
	data_to_reg(0x00,Sport0_Tx_Words1)	/* MSB 16bit Tx */
	data_to_reg(0x00,Sport0_Rx_Words1)	/*           Rx */
	rts;
codec_init_command_mode:
	interrupt_disable
	serial_port_0_disable
	autobuf_port_0_disable
	data_to_mem(0x08,fifo_tx+0)	/* olb=1, clb=0(control) */
	data_to_mem(0x1c,fifo_tx+1)	/* 32KHz, Stereo, 16bit */
	data_to_mem(0x9a,fifo_tx+2)	/* 256bit, x1, gen.clk */
	data_to_mem(0x00,fifo_tx+3)	/* (reserved) */
	data_to_mem(0xc0,fifo_tx+4)	/* (reserved) */
	data_to_mem(0x00,fifo_tx+6)	/* (reserved) */
	I0=^fifo_tx; M0=1; L0=8; 
	I1=^fifo_rx; M1=1; L1=8; 
	data_to_reg(0xc707,Sport0_Ctrl_Reg)	/* CODEC --> Setting Mode */
	direct_tx_port_0(I0,M0)
	autobuf_port_0_enable			/* tx=I0, rx=I1 */
	serial_port_0_enable
	interrupt_s0_rx_enable
loop_1:
	waiting_for_interrupt
	call check_1;
	if ne jump loop_1;
	interrupt_s0_tx_enable
	data_to_mem(0x000C,fifo_tx+0)		/* clb set */
	waiting_for_interrupt
	waiting_for_interrupt
	waiting_for_interrupt
	rts;
check_1: 
	AX0=DM(fifo_rx+0); AY0=0x04; AR=AX0 and AY0;
	if ne jump chk_exit;
	AX0=DM(fifo_tx+1); AY0=DM(fifo_rx+1); AR=AX0-AY0;
	if ne jump chk_exit;
	AX0=DM(fifo_tx+2); AY0=DM(fifo_rx+2); AF=AX0 xor AY0;
	AX0=0xFF7F; AR=AX0 and AF;
chk_exit:
	rts;
codec_init_data_mode:
	interrupt_disable
	serial_port_0_disable
	autobuf_port_0_disable
	data_to_mem(0x00,fifo_tx+0)	/* (dummy) */
	data_to_mem(0x00,fifo_tx+1)	/*    |    */
	data_to_mem(0x00,fifo_tx+2)	/*    |    */
	data_to_mem(0x00,fifo_tx+3)	/* (dummy) */
	data_to_mem(0xc0,fifo_tx+4)	/* Output Enable, Lch : 0db ATT */
	data_to_mem(0x00,fifo_tx+5)	/*                Rch : 0db ATT */
	data_to_mem(0xc6,fifo_tx+6)	/* Input <- Line, Lch : gain 9dB */
	data_to_mem(0xf6,fifo_tx+7)	/*                Rch : gain 9dB */
	I0=^fifo_tx; M0=1; L0=8;
	I1=^fifo_rx; M1=1; L1=8;
	I2=^fifo_tx; M2=1; L2=2;		/* Data Buffer for Tx (L) */
	I3=^fifo_rx; M3=1; L3=2;		/*                 Rx (L) */
	data_to_reg(0x8607,Sport0_Ctrl_Reg)	/* CODEC --> Running Mode */
	data_to_reg(dc,codec_ctrl)		/* Change to Data Mode */
	direct_tx_port_0(I0,M0)
	autobuf_port_0_enable			/* tx=I0, rx=I1 */
	serial_port_0_enable
	interrupt_s0_rx_enable
	rts;


.VAR/DM/RAM/ABS=0x1000/CIRC	dac_buf[0x1000];
.VAR/DM/RAM/ABS=0x2000		dac_amt;
.VAR/DM/RAM/ABS=0x2010/CIRC	s0_ctl_send[8];
.VAR/DM/RAM/ABS=0x2020/CIRC	s0_ctl_recv[8];
.VAR/DM/RAM/ABS=0x2030/CIRC	s0_dat_send[8];
.VAR/DM/RAM/ABS=0x2040/CIRC	s0_dat_recv[8];

#define	ts1	0
#define	ts2	1
#define	ts3	2
#define	ts4	3
#define	ts5	4
#define	ts6	5
#define	ts7	6
#define	ts8	7

{ interupt vector table }
        jump start; RTI; RTI; RTI;	{Reset Vector}    
	RTI; RTI; RTI; RTI;		{irq2}
        jump s0send; RTI; RTI; RTI;	{sport0 TX}
        jump s0recv; RTI; RTI; RTI;	{sport0 RX}
        RTI; RTI; RTI; RTI;		{irq0}
        RTI; RTI; RTI; RTI;		{irq1}
        RTI; RTI; RTI; RTI;		{timer}

#include <dsp_tail.h>;

start:
	ifc=0x3f; IMASK=0x00;			/* int disable */
	AX0 = 0x0408; DM(Sys_Ctrl_Reg) = AX0;	/* sport0 disable */
	AX0 = 1; DM(Dm_Wait_Reg)  = AX0;
	
initcodec:
	AX0=0x00ff; DM(Sport0_Tx_Words0)=AX0;	/* 64bit */ 
	AX0=0x00ff; DM(Sport0_Rx_Words0)=AX0;	/* 64bit */
	AX0=0x0000; DM(Sport0_Tx_Words1)=AX0;
	AX0=0x0000; DM(Sport0_Rx_Words1)=AX0;
	AX0=0xc707; DM(Sport0_Ctrl_Reg)=AX0;	/* rfs send mode */
	AX0=0x0000; DM(Sport0_Sclkdiv)=AX0;
	AX0=255;   DM(Sport0_Rfsdiv)=AX0;	/* multichannel,256bit */
{ control mode timeslot }
	AX0=0x8;	DM(s0_ctl_send+ts1)=AX0; /* olb=1,clb=0 */
/*	AX0=0x0;	DM(s0_ctl_send+ts1)=AX0;    olb=0,clb=0 */
	AX0=0x34;	DM(s0_ctl_send+ts2)=AX0; /* 48KHz,st,16bit */
	AX0=0x9a;	DM(s0_ctl_send+ts3)=AX0; /* 256b,x1,gen.clk */
	AX0=0;		DM(s0_ctl_send+ts4)=AX0;
	AX0=0xc0;	DM(s0_ctl_send+ts5)=AX0;
	AX0=0;		DM(s0_ctl_send+ts6)=AX0;
	AX0=0;		DM(s0_ctl_send+ts7)=AX0;
	AX0=0;		DM(s0_ctl_send+ts8)=AX0;
	AX0=0xffff;	DM(s0_ctl_recv+ts1)=AX0;
	AX0=0xffff;	DM(s0_ctl_recv+ts2)=AX0;
	AX0=0xffff;	DM(s0_ctl_recv+ts3)=AX0;
{ data time slot }	
	AX0=0x0;	DM(s0_dat_send+ts1)=AX0;
	AX0=0x0;	DM(s0_dat_send+ts2)=AX0;
	AX0=0x0;	DM(s0_dat_send+ts3)=AX0;
	AX0=0x0;	DM(s0_dat_send+ts4)=AX0;
	AX0=0xc5;	DM(s0_dat_send+ts5)=AX0;
	AX0=0x05;	DM(s0_dat_send+ts6)=AX0;
	AX0=0xd0;	DM(s0_dat_send+ts7)=AX0;
	AX0=0xf0;	DM(s0_dat_send+ts8)=AX0;
	AX0=0x0;	DM(s0_dat_recv+ts1)=AX0;
	AX0=0x0;	DM(s0_dat_recv+ts2)=AX0;
	AX0=0x0;	DM(s0_dat_recv+ts3)=AX0;
	AX0=0x0;	DM(s0_dat_recv+ts4)=AX0;
	AX0=0x0;	DM(s0_dat_recv+ts5)=AX0;
	AX0=0x0;	DM(s0_dat_recv+ts6)=AX0;
	AX0=0x0;	DM(s0_dat_recv+ts7)=AX0;
	AX0=0x0;	DM(s0_dat_recv+ts8)=AX0;
{ control mode set }
	I0 =^s0_ctl_send; M0=1; L0=8; 
	I1 =^s0_ctl_recv; M1=1; L1=8; 
	AX0 =DM(I0,M0); TX0=AX0;
	AX0=0x17; 
	SI = RX0; 
	DM(Sport0_Autobuf_Ctrl)=AX0;
	AX0 = 0x1408; 
	SI = RX0; 
	DM(Sys_Ctrl_Reg) = AX0;
	IMASK=0x08;				/* s0 rx int enb */
loop1:	idle;
	CALL control_mode_chk;
	IF NE jump loop1;
	IMASK=0x10;				/* s0 tx int enb */
	AX0=0x0C; DM(s0_ctl_send+ts1)=AX0;	/* clb set */
	idle;
	idle;
	IMASK=0;
{ dsp set data mode }	
	AX0=0x8607; DM(Sport0_Ctrl_Reg)=AX0;
	AX0=0x00ff; DM(Sport0_Tx_Words0)=AX0; 
	AX0=0x00ff; DM(Sport0_Rx_Words0)=AX0; 
	AX0=0x0000; DM(Sport0_Tx_Words1)=AX0;
	AX0=0x0000; DM(Sport0_Rx_Words1)=AX0;
{ }
	I2 =^dac_buf; M2=1; L2=DM(dac_amt); 
	SI =DM(dac_amt); SR=LSHIFT SI BY -1 (LO);
	AY0=^dac_buf; AR=SR0+AY0;
	I3=AR; M3=1; L3=DM(dac_amt); 
	I0 =^s0_dat_send; M0=1; L0=8; 
	I1 =^s0_dat_recv; M1=1; L1=8; 
	AX0=0x16; SI = RX0; 
	DM(Sport0_Autobuf_Ctrl)=AX0;
	CALL sin_dat_set;
	IMASK=0x10;			
	AX0=dc;	DM(codec_ctrl)=AX0;	/* set dc to high */
loop2:	idle;
	CALL sin_dat_set;
	jump loop2;
	
control_mode_chk: 
	{ for CS4215 rev. 1 }
	AX0=DM(s0_ctl_recv+ts1);
	AY0=0x04; AR=AX0 and AY0;
	IF NE jump chk1;
	AX0=DM(s0_ctl_send+ts2);
	AY0=DM(s0_ctl_recv+ts2);
	AR=AX0-AY0;
	IF NE jump chk1;
	AX0=DM(s0_ctl_send+ts3);
	AY0=DM(s0_ctl_recv+ts3);
	AF=AX0 xor AY0;
	AX0=0xFF7F; AR=AX0 and AF;
chk1:	rts;

sin_dat_set:
	SI=DM(I2,M2);
	SR=LSHIFT SI BY -8 (LO);
	DM(s0_dat_send+ts1)=SR0;
	DM(s0_dat_send+ts2)=SI;
	SI=DM(I3,M3);
	SR=LSHIFT SI BY -8 (LO);
	DM(s0_dat_send+ts3)=SR0;
	DM(s0_dat_send+ts4)=SI;
	rts;

s0send:	rti;
s0recv:	rti;

.ENDMOD;

=============================================================================


.MODULE/RAM/BOOT = 0/ABS = 0	selftest;

.CONST dm_test_top = 0x0820;
.CONST pm_test_top = 0x1000;
.CONST complete	= 0;
.CONST dm_fail	= 1;
.CONST pm_fail	= 2;
.CONST erradr	= 0x0812;

.const  Sys_Ctrl_Reg= 		    0x3fff;
.const  Dm_Wait_Reg= 	            0x3ffe;
.const  Tperiod_Reg=                0x3ffd;
.const  Tcount_Reg=                 0x3ffc;
.const  Tscale_Reg=                 0x3ffb;
.const  Sport0_Rx_Words1=           0x3ffa;
.const  Sport0_Rx_Words0=           0x3ff9;
.const  Sport0_Tx_Words1=           0x3ff8;
.const  Sport0_Tx_Words0=           0x3ff7;
.const  Sport0_Ctrl_Reg=            0x3ff6;
.const  Sport0_Sclkdiv=             0x3ff5;
.const  Sport0_Rfsdiv=              0x3ff4;
.const  Sport0_Autobuf_Ctrl=        0x3ff3;
.const  Sport1_Ctrl_Reg=            0x3ff2;
.const  Sport1_Sclkdiv=             0x3ff1;
.const  Sport1_Rfsdiv=              0x3ff0;
.const  Sport1_Autobuf_Ctrl=        0x3fef;

{ SYSTEM I/O ADDRESS DEFINES }
.const  Sys_Ctrl_Reg= 		    0x3fff;
.const  Dm_Wait_Reg= 	            0x3ffe;
.const  Tperiod_Reg=                0x3ffd;
.const  Tcount_Reg=                 0x3ffc;
.const  Tscale_Reg=                 0x3ffb;
.const  Sport0_Rx_Words1=           0x3ffa;
.const  Sport0_Rx_Words0=           0x3ff9;
.const  Sport0_Tx_Words1=           0x3ff8;
.const  Sport0_Tx_Words0=           0x3ff7;
.const  Sport0_Ctrl_Reg=            0x3ff6;
.const  Sport0_Sclkdiv=             0x3ff5;
.const  Sport0_Rfsdiv=              0x3ff4;
.const  Sport0_Autobuf_Ctrl=        0x3ff3;
.const  Sport1_Ctrl_Reg=            0x3ff2;
.const  Sport1_Sclkdiv=             0x3ff1;
.const  Sport1_Rfsdiv=              0x3ff0;
.const  Sport1_Autobuf_Ctrl=        0x3fef;

.CONST comcrdy	= 0x0803;
.CONST comdrdy	= 0x0804;
.CONST cpudt 	= 0x0810;
.CONST dspdt	= 0x0811;

{ BOAD REGISTERS }
.CONST hs_readonly	= 0x0600;
.CONST handshake	= 0x0700;
.CONST dipswitch	= 0x0400;
.CONST codec_ctrl	= 0x0400;

{ CONTROLE BITS }
.CONST d2c	= 0x2000;
.CONST c2d	= 0x1000;
.CONST s8	= 0x8000;
.CONST s4	= 0x4000;
.CONST s2	= 0x2000;
.CONST s1	= 0x1000;
.CONST dc	= 0x1000;
.CONST c2denb	= 0x2000;
.CONST extenb	= 0x4000;

{ MEMORY STRUCTURE }
.CONST	dm_top		= 0x0800;
.CONST	dm_bottom	= 0x3BFF;
.CONST	pm_top		= 0x0000;
.CONST	pm_bottom	= 0x3FFF;

.CONST	ext_dm_top	= 0x0800;
.CONST	ext_dm_bottom	= 0x37FF;
.CONST	int_dm_top	= 0x3800;
.CONST	int_dm_bottom	= 0x3BFF;
.CONST	ext_pm_top	= 0x0800;
.CONST	ext_pm_bottom	= 0x3FFF;
.CONST	int_pm_top	= 0x0000;
.CONST	int_pm_bottom	= 0x07FF;

{ TERMINATE PROGRAM }
.CONST	end_of_prog	= 0x001D;

/******************** Special Macro Defines ********************/
#define data_to_mem(data,memory)	AX0=data; DM(memory)=AX0;
#define data_to_reg(data,register)	AX0=data; DM(register)=AX0;
#define interrupt_disable		IFC=0x3f; IMASK=0x00;
#define interrupt_s0_rx_enable		IFC=0x3f; IMASK=0x08;
#define interrupt_s0_tx_enable		IFC=0x3f; IMASK=0x10;
#define waiting_for_interrupt		idle;
#define direct_tx_port_0(i_reg,m_reg)	AX0=DM(i_reg,m_reg); TX0=AX0;
#define serial_port_0_disable		data_to_reg(0x0408,Sys_Ctrl_Reg)
#define serial_port_0_enable		data_to_reg(0x1408,Sys_Ctrl_Reg)
#define autobuf_port_0_disable		data_to_reg(0x0000,Sport0_Autobuf_Ctrl)
#define autobuf_port_0_enable		data_to_reg(0x0017,Sport0_Autobuf_Ctrl)
.MACRO codec_to_AR_reg_mono;
	SR0=DM(I3,M3); AY0=DM(I3,M3);
	SR=lshift SR0 by 8 (lo); AR=SR0 or AY0;
.ENDMACRO;
.MACRO SR0_reg_to_codec_mono;
	AY0=0xff; AR=SR0 and AY0; SR=lshift SR0 by -8 (lo);
	DM(I2,M2)=SR0; DM(I2,M2)=AR;
.ENDMACRO;

/******************** Buffer Memory Defines ********************/
.VAR/DM/RAM/ABS=0x0900/CIRC	fifo_tx[8];
.VAR/DM/RAM/ABS=0x0910/CIRC	fifo_rx[8];

/******************** Reset Vectors Defines ********************/
jump start;	nop; nop; nop;	{Reset Vector}
	RTI;	nop; nop; nop;	{irq2}
	RTI;	nop; nop; nop;	{sport0 TX}
	RTI;	nop; nop; nop;	{sport0 RX}
	RTI;	nop; nop; nop;	{irq0}
	RTI;	nop; nop; nop;	{irq1}
	RTI;	nop; nop; nop;	{timer}

/******************** Common Subroutines ********************/
codec_initialize:
	call codec_system_init;
	call codec_init_command_mode;
	call codec_init_data_mode;
	rts;
codec_system_init:
	data_to_reg(0x01,Dm_Wait_Reg)		/* 1 wait */
	data_to_reg(0xff,Sport0_Rfsdiv)		/* Multi-ch, 256bit */
	data_to_reg(0x00,Sport0_Sclkdiv)	/* divide rate */
	data_to_reg(0xff,Sport0_Tx_Words0)	/* LSB 16bit Tx */
	data_to_reg(0xff,Sport0_Rx_Words0)	/*           Rx */
	data_to_reg(0x00,Sport0_Tx_Words1)	/* MSB 16bit Tx */
	data_to_reg(0x00,Sport0_Rx_Words1)	/*           Rx */
	rts;
codec_init_command_mode:
	interrupt_disable
	serial_port_0_disable
	autobuf_port_0_disable
	data_to_mem(0x08,fifo_tx+0)	/* olb=1, clb=0(control) */
	data_to_mem(0x1c,fifo_tx+1)	/* 32KHz, Stereo, 16bit */
	data_to_mem(0x9a,fifo_tx+2)	/* 256bit, x1, gen.clk */
	data_to_mem(0x00,fifo_tx+3)	/* (reserved) */
	data_to_mem(0xc0,fifo_tx+4)	/* (reserved) */
	data_to_mem(0x00,fifo_tx+6)	/* (reserved) */
	I0=^fifo_tx; M0=1; L0=8; 
	I1=^fifo_rx; M1=1; L1=8; 
	data_to_reg(0xc707,Sport0_Ctrl_Reg)	/* CODEC --> Setting Mode */
	direct_tx_port_0(I0,M0)
	autobuf_port_0_enable			/* tx=I0, rx=I1 */
	serial_port_0_enable
	interrupt_s0_rx_enable
loop_1:
	waiting_for_interrupt
	call check_1;
	if ne jump loop_1;
	interrupt_s0_tx_enable
	data_to_mem(0x000C,fifo_tx+0)		/* clb set */
	waiting_for_interrupt
	waiting_for_interrupt
	waiting_for_interrupt
	rts;
check_1: 
	AX0=DM(fifo_rx+0); AY0=0x04; AR=AX0 and AY0;
	if ne jump chk_exit;
	AX0=DM(fifo_tx+1); AY0=DM(fifo_rx+1); AR=AX0-AY0;
	if ne jump chk_exit;
	AX0=DM(fifo_tx+2); AY0=DM(fifo_rx+2); AF=AX0 xor AY0;
	AX0=0xFF7F; AR=AX0 and AF;
chk_exit:
	rts;
codec_init_data_mode:
	interrupt_disable
	serial_port_0_disable
	autobuf_port_0_disable
	data_to_mem(0x00,fifo_tx+0)	/* (dummy) */
	data_to_mem(0x00,fifo_tx+1)	/*    |    */
	data_to_mem(0x00,fifo_tx+2)	/*    |    */
	data_to_mem(0x00,fifo_tx+3)	/* (dummy) */
	data_to_mem(0xc0,fifo_tx+4)	/* Output Enable, Lch : 0db ATT */
	data_to_mem(0x00,fifo_tx+5)	/*                Rch : 0db ATT */
	data_to_mem(0xc6,fifo_tx+6)	/* Input <- Line, Lch : gain 9dB */
	data_to_mem(0xf6,fifo_tx+7)	/*                Rch : gain 9dB */
	I0=^fifo_tx; M0=1; L0=8;
	I1=^fifo_rx; M1=1; L1=8;
	I2=^fifo_tx; M2=1; L2=2;		/* Data Buffer for Tx (L) */
	I3=^fifo_rx; M3=1; L3=2;		/*                 Rx (L) */
	data_to_reg(0x8607,Sport0_Ctrl_Reg)	/* CODEC --> Running Mode */
	data_to_reg(dc,codec_ctrl)		/* Change to Data Mode */
	direct_tx_port_0(I0,M0)
	autobuf_port_0_enable			/* tx=I0, rx=I1 */
	serial_port_0_enable
	interrupt_s0_rx_enable
	rts;


{ interupt vector table }
        JUMP start; RTI; RTI; RTI;      {Reset Vector}    
	JUMP handler; RTI; RTI; RTI;	{irq2}
        RTI; RTI; RTI; RTI;             {sport0 TX}
        RTI; RTI; RTI; RTI;             {sport0 RX}
        RTI; RTI; RTI; RTI;             {irq0}
        RTI; RTI; RTI; RTI;             {irq1}
        RTI; RTI; RTI; RTI;             {timer}

#include <dsp_tail.h>;

start:
	AX0 = 0x0408; DM(Sys_Ctrl_Reg) = AX0;
	AX0 = 1; DM(Dm_Wait_Reg)  = AX0;
	
dm_5555:
	SI = 0x5555;
	CALL dmfill;
	SI = 0x1234;	{ jam }
	PX = 0x67;
	CALL pmfill;
	AX0 = 0x5555;
	CALL dmcheck;
	AR = PASS AX1;
	IF EQ JUMP dm_AAAA;
		AX0 = 0; DM(comdrdy) = AX0; DM(comcrdy) = AX0;
		DM(erradr) = AY1;
		SI = dm_fail; CALL put_wd;
		IDLE;
dm_AAAA:
	SI = 0xAAAA;
	CALL dmfill;
	SI = 0xfedc;	{ jam }
	PX = 0xb9;
	CALL pmfill;
	AX0 = 0xAAAA;
	CALL dmcheck;
	AR = PASS AX1;
	IF EQ JUMP dm_end;
		AX0 = 0; DM(comdrdy) = AX0; DM(comcrdy) = AX0;
		DM(comcrdy) = AX0;
		DM(erradr) = AY1;
		SI = dm_fail; CALL put_wd;
		IDLE;
dm_end:
pm_5555:
	SI = 0x5555;
	PX = 0x55;
	CALL pmfill;
	SI = 0x1234;	{ JAM }
	CALL dmfill;
	AX0 = 0x5555;
	PX = 0x55;
	CALL pmcheck;
	AR = PASS AX1;
	IF EQ JUMP pm_AAAA;
		AX0 = 0; DM(comdrdy) = AX0; DM(comcrdy) = AX0;
		DM(erradr) = AY1;
		SI = pm_fail; CALL put_wd;
		IDLE;
pm_AAAA:
	SI = 0xAAAA;
	PX = 0xAA;
	CALL pmfill;
	SI = 0xfedc;	{ JAM }
	CALL dmfill;
	AX0 = 0xAAAA;
	PX = 0xAA;
	CALL pmcheck;
	AR = PASS AX1;
	IF EQ JUMP pm_end;
		AX0 = 0; DM(comdrdy) = AX0; DM(comcrdy) = AX0;
		DM(erradr) = AY1;
		SI = pm_fail; CALL put_wd;
		IDLE;
pm_end:
	AX0 = 0; DM(comdrdy) = AX0; DM(comcrdy) = AX0;
	DM(erradr) = AY1;
	SI = complete; CALL put_wd;
int_cpu:
	CALL intcheck;

int_dsp:
	CALL intdsp;

	IDLE;
{--------------------}
{ fill data memory with SI }
dmfill:
	I0 = dm_test_top; M0 = 1; L0 = 0;
	CNTR = dm_bottom - dm_test_top + 1;
	DO fill_0 UNTIL CE;
fill_0:		DM(I0, M0) = SI;
	RTS;

{--------------------}
{ check data memory with AX0 }
dmcheck:
	I0 = dm_test_top; M0 = 1; L0 = 0;
	AR = dm_bottom - dm_test_top + 1;
	AF = PASS AR;
check_0:	AY0 = DM(I0, M0);
		AR = AX0 - AY0;
		IF EQ JUMP continue_0;
			AX1 = dm_bottom + 1;
			AR = AX1 - AF; AY1 = AR;
			AX1 = 0xFFFF;
			RTS;
continue_0:	AF = AF - 1;
		IF NE JUMP check_0;
	AX1 = dm_bottom ;
	AR = AX1 - AF; AY1 = AR;
	AX1 = 0;
	RTS;

{--------------------}
{ fill program memory with SI }
pmfill:
	I4 = pm_test_top; M4 = 1; L4 = 0;
	CNTR = pm_bottom - pm_test_top + 1;
	DO fill_1 UNTIL CE;
fill_1:		PM(I4, M4) = SI;
	RTS;

{--------------------}
{ check program memory with AX0 }
pmcheck:
	AX1 = PX;
	I4 = pm_test_top; M4 = 1; L4 = 0;
	AR = pm_bottom - pm_test_top + 1;
	AF = PASS AR;
check_1:	AY0 = PM(I4, M4);
		AR = AX0 - AY0;
		IF NE JUMP else_1;

		AY0 = PX;
		AR = AX1 - AY0;
		IF NE JUMP else_1;

continue_1:	AF = AF - 1;
		IF NE JUMP check_1;
	AX1 = pm_bottom ;
	AR = AX1 - AF; AY1 = AR;
	AX1 = 0;
	RTS;

else_1: AX1 = pm_bottom + 1;
	AR = AX1 - AF; AY1 = AR;
	AX1 = 0xFFFF;
	RTS;

{--------------------}
{ check Interrupt to CPU }
intcheck:
	AX1 = 0;   DM(handshake) = AX1; /* make int signal to low */
	CALL get_wd;	/* wait for CPU executes put_word(NULL); */

	AX1 = d2c; DM(handshake) = AX1; /* make int signal hi */
	RTS;

{--------------------}
{ check Interrupt to DSP }
intdsp:
	AX0=c2denb; DM(codec_ctrl)=AX0;
	IFC=0x20;
	CALL put_wd; /* dummy data */
	IMASK = 0x20;
	IDLE;
	AX0=0; DM(codec_ctrl)=AX0;
	IMASK = 0;
	RTS;

{--------------------}
{ Interrupt handler }
handler:
	AX1 = DM(handshake);
	RTI;

.ENDMOD;

=============================================================================


.MODULE/RAM/BOOT=0/ABS=0	test;

.const  Sys_Ctrl_Reg= 		    0x3fff;
.const  Dm_Wait_Reg= 	            0x3ffe;
.const  Tperiod_Reg=                0x3ffd;
.const  Tcount_Reg=                 0x3ffc;
.const  Tscale_Reg=                 0x3ffb;
.const  Sport0_Rx_Words1=           0x3ffa;
.const  Sport0_Rx_Words0=           0x3ff9;
.const  Sport0_Tx_Words1=           0x3ff8;
.const  Sport0_Tx_Words0=           0x3ff7;
.const  Sport0_Ctrl_Reg=            0x3ff6;
.const  Sport0_Sclkdiv=             0x3ff5;
.const  Sport0_Rfsdiv=              0x3ff4;
.const  Sport0_Autobuf_Ctrl=        0x3ff3;
.const  Sport1_Ctrl_Reg=            0x3ff2;
.const  Sport1_Sclkdiv=             0x3ff1;
.const  Sport1_Rfsdiv=              0x3ff0;
.const  Sport1_Autobuf_Ctrl=        0x3fef;

{ SYSTEM I/O ADDRESS DEFINES }
.const  Sys_Ctrl_Reg= 		    0x3fff;
.const  Dm_Wait_Reg= 	            0x3ffe;
.const  Tperiod_Reg=                0x3ffd;
.const  Tcount_Reg=                 0x3ffc;
.const  Tscale_Reg=                 0x3ffb;
.const  Sport0_Rx_Words1=           0x3ffa;
.const  Sport0_Rx_Words0=           0x3ff9;
.const  Sport0_Tx_Words1=           0x3ff8;
.const  Sport0_Tx_Words0=           0x3ff7;
.const  Sport0_Ctrl_Reg=            0x3ff6;
.const  Sport0_Sclkdiv=             0x3ff5;
.const  Sport0_Rfsdiv=              0x3ff4;
.const  Sport0_Autobuf_Ctrl=        0x3ff3;
.const  Sport1_Ctrl_Reg=            0x3ff2;
.const  Sport1_Sclkdiv=             0x3ff1;
.const  Sport1_Rfsdiv=              0x3ff0;
.const  Sport1_Autobuf_Ctrl=        0x3fef;

.CONST comcrdy	= 0x0803;
.CONST comdrdy	= 0x0804;
.CONST cpudt 	= 0x0810;
.CONST dspdt	= 0x0811;

{ BOAD REGISTERS }
.CONST hs_readonly	= 0x0600;
.CONST handshake	= 0x0700;
.CONST dipswitch	= 0x0400;
.CONST codec_ctrl	= 0x0400;

{ CONTROLE BITS }
.CONST d2c	= 0x2000;
.CONST c2d	= 0x1000;
.CONST s8	= 0x8000;
.CONST s4	= 0x4000;
.CONST s2	= 0x2000;
.CONST s1	= 0x1000;
.CONST dc	= 0x1000;
.CONST c2denb	= 0x2000;
.CONST extenb	= 0x4000;

{ MEMORY STRUCTURE }
.CONST	dm_top		= 0x0800;
.CONST	dm_bottom	= 0x3BFF;
.CONST	pm_top		= 0x0000;
.CONST	pm_bottom	= 0x3FFF;

.CONST	ext_dm_top	= 0x0800;
.CONST	ext_dm_bottom	= 0x37FF;
.CONST	int_dm_top	= 0x3800;
.CONST	int_dm_bottom	= 0x3BFF;
.CONST	ext_pm_top	= 0x0800;
.CONST	ext_pm_bottom	= 0x3FFF;
.CONST	int_pm_top	= 0x0000;
.CONST	int_pm_bottom	= 0x07FF;

{ TERMINATE PROGRAM }
.CONST	end_of_prog	= 0x001D;

/******************** Special Macro Defines ********************/
#define data_to_mem(data,memory)	AX0=data; DM(memory)=AX0;
#define data_to_reg(data,register)	AX0=data; DM(register)=AX0;
#define interrupt_disable		IFC=0x3f; IMASK=0x00;
#define interrupt_s0_rx_enable		IFC=0x3f; IMASK=0x08;
#define interrupt_s0_tx_enable		IFC=0x3f; IMASK=0x10;
#define waiting_for_interrupt		idle;
#define direct_tx_port_0(i_reg,m_reg)	AX0=DM(i_reg,m_reg); TX0=AX0;
#define serial_port_0_disable		data_to_reg(0x0408,Sys_Ctrl_Reg)
#define serial_port_0_enable		data_to_reg(0x1408,Sys_Ctrl_Reg)
#define autobuf_port_0_disable		data_to_reg(0x0000,Sport0_Autobuf_Ctrl)
#define autobuf_port_0_enable		data_to_reg(0x0017,Sport0_Autobuf_Ctrl)
.MACRO codec_to_AR_reg_mono;
	SR0=DM(I3,M3); AY0=DM(I3,M3);
	SR=lshift SR0 by 8 (lo); AR=SR0 or AY0;
.ENDMACRO;
.MACRO SR0_reg_to_codec_mono;
	AY0=0xff; AR=SR0 and AY0; SR=lshift SR0 by -8 (lo);
	DM(I2,M2)=SR0; DM(I2,M2)=AR;
.ENDMACRO;

/******************** Buffer Memory Defines ********************/
.VAR/DM/RAM/ABS=0x0900/CIRC	fifo_tx[8];
.VAR/DM/RAM/ABS=0x0910/CIRC	fifo_rx[8];

/******************** Reset Vectors Defines ********************/
jump start;	nop; nop; nop;	{Reset Vector}
	RTI;	nop; nop; nop;	{irq2}
	RTI;	nop; nop; nop;	{sport0 TX}
	RTI;	nop; nop; nop;	{sport0 RX}
	RTI;	nop; nop; nop;	{irq0}
	RTI;	nop; nop; nop;	{irq1}
	RTI;	nop; nop; nop;	{timer}

/******************** Common Subroutines ********************/
codec_initialize:
	call codec_system_init;
	call codec_init_command_mode;
	call codec_init_data_mode;
	rts;
codec_system_init:
	data_to_reg(0x01,Dm_Wait_Reg)		/* 1 wait */
	data_to_reg(0xff,Sport0_Rfsdiv)		/* Multi-ch, 256bit */
	data_to_reg(0x00,Sport0_Sclkdiv)	/* divide rate */
	data_to_reg(0xff,Sport0_Tx_Words0)	/* LSB 16bit Tx */
	data_to_reg(0xff,Sport0_Rx_Words0)	/*           Rx */
	data_to_reg(0x00,Sport0_Tx_Words1)	/* MSB 16bit Tx */
	data_to_reg(0x00,Sport0_Rx_Words1)	/*           Rx */
	rts;
codec_init_command_mode:
	interrupt_disable
	serial_port_0_disable
	autobuf_port_0_disable
	data_to_mem(0x08,fifo_tx+0)	/* olb=1, clb=0(control) */
	data_to_mem(0x1c,fifo_tx+1)	/* 32KHz, Stereo, 16bit */
	data_to_mem(0x9a,fifo_tx+2)	/* 256bit, x1, gen.clk */
	data_to_mem(0x00,fifo_tx+3)	/* (reserved) */
	data_to_mem(0xc0,fifo_tx+4)	/* (reserved) */
	data_to_mem(0x00,fifo_tx+6)	/* (reserved) */
	I0=^fifo_tx; M0=1; L0=8; 
	I1=^fifo_rx; M1=1; L1=8; 
	data_to_reg(0xc707,Sport0_Ctrl_Reg)	/* CODEC --> Setting Mode */
	direct_tx_port_0(I0,M0)
	autobuf_port_0_enable			/* tx=I0, rx=I1 */
	serial_port_0_enable
	interrupt_s0_rx_enable
loop_1:
	waiting_for_interrupt
	call check_1;
	if ne jump loop_1;
	interrupt_s0_tx_enable
	data_to_mem(0x000C,fifo_tx+0)		/* clb set */
	waiting_for_interrupt
	waiting_for_interrupt
	waiting_for_interrupt
	rts;
check_1: 
	AX0=DM(fifo_rx+0); AY0=0x04; AR=AX0 and AY0;
	if ne jump chk_exit;
	AX0=DM(fifo_tx+1); AY0=DM(fifo_rx+1); AR=AX0-AY0;
	if ne jump chk_exit;
	AX0=DM(fifo_tx+2); AY0=DM(fifo_rx+2); AF=AX0 xor AY0;
	AX0=0xFF7F; AR=AX0 and AF;
chk_exit:
	rts;
codec_init_data_mode:
	interrupt_disable
	serial_port_0_disable
	autobuf_port_0_disable
	data_to_mem(0x00,fifo_tx+0)	/* (dummy) */
	data_to_mem(0x00,fifo_tx+1)	/*    |    */
	data_to_mem(0x00,fifo_tx+2)	/*    |    */
	data_to_mem(0x00,fifo_tx+3)	/* (dummy) */
	data_to_mem(0xc0,fifo_tx+4)	/* Output Enable, Lch : 0db ATT */
	data_to_mem(0x00,fifo_tx+5)	/*                Rch : 0db ATT */
	data_to_mem(0xc6,fifo_tx+6)	/* Input <- Line, Lch : gain 9dB */
	data_to_mem(0xf6,fifo_tx+7)	/*                Rch : gain 9dB */
	I0=^fifo_tx; M0=1; L0=8;
	I1=^fifo_rx; M1=1; L1=8;
	I2=^fifo_tx; M2=1; L2=2;		/* Data Buffer for Tx (L) */
	I3=^fifo_rx; M3=1; L3=2;		/*                 Rx (L) */
	data_to_reg(0x8607,Sport0_Ctrl_Reg)	/* CODEC --> Running Mode */
	data_to_reg(dc,codec_ctrl)		/* Change to Data Mode */
	direct_tx_port_0(I0,M0)
	autobuf_port_0_enable			/* tx=I0, rx=I1 */
	serial_port_0_enable
	interrupt_s0_rx_enable
	rts;

.VAR/DM/RAM/ABS=0x2010/CIRC	s0_ctl_send[8]; /* 2010-2017 */
.VAR/DM/RAM/ABS=0x2020/CIRC	s0_ctl_recv[8]; /* 2020-2027 */
.VAR/DM/RAM/ABS=0x2030/CIRC	s0_dat_send[8]; /* 2030-2037 */
.VAR/DM/RAM/ABS=0x2040/CIRC	s0_dat_recv[8]; /* 2040-2047 */

#define	ts1	0
#define	ts2	1
#define	ts3	2
#define	ts4	3
#define	ts5	4
#define	ts6	5
#define	ts7	6
#define	ts8	7

{ interupt vector table }
        jump start; RTI; RTI; RTI;	{Reset Vector}
	RTI; RTI; RTI; RTI;		{irq2}
        jump s0send; RTI; RTI; RTI;	{sport0 TX}
        jump s0recv; RTI; RTI; RTI;	{sport0 RX}
        RTI; RTI; RTI; RTI;		{irq0}
        RTI; RTI; RTI; RTI;		{irq1}
        RTI; RTI; RTI; RTI;		{timer}

#include <dsp_tail.h>;

start:
	ifc=0x3f; IMASK=0x00;			/* int disable */
	AX0=0x0408;	DM(Sys_Ctrl_Reg) = AX0;	/* sport0 disable */
	AX0=0x0001;	DM(Dm_Wait_Reg)  = AX0;
initcodec:
	AX0=0x00ff;	DM(Sport0_Tx_Words0)=AX0;	/* 64bit */ 
	AX0=0x00ff;	DM(Sport0_Rx_Words0)=AX0;	/* 64bit */
	AX0=0x0000;	DM(Sport0_Tx_Words1)=AX0;
	AX0=0x0000;	DM(Sport0_Rx_Words1)=AX0;
	AX0=0xc707;	DM(Sport0_Ctrl_Reg)=AX0;	/* rfs send mode */
	AX0=0x0000;	DM(Sport0_Sclkdiv)=AX0;
	AX0=0x00ff;	DM(Sport0_Rfsdiv)=AX0;		/* multi-ch,256bit */
{ control mode timeslot }
	AX0=0x8;	DM(s0_ctl_send+ts1)=AX0; /* olb=1,clb=0 */
	AX0=0x34;	DM(s0_ctl_send+ts2)=AX0; /* 48KHz,st,16bit */
	AX0=0x9a;	DM(s0_ctl_send+ts3)=AX0; /* 256b,x1,gen.clk */
	AX0=0;		DM(s0_ctl_send+ts4)=AX0;
	AX0=0xc0;	DM(s0_ctl_send+ts5)=AX0;
	AX0=0;		DM(s0_ctl_send+ts6)=AX0;
	AX0=0;		DM(s0_ctl_send+ts7)=AX0;
	AX0=0;		DM(s0_ctl_send+ts8)=AX0;
	AX0=0xffff;	DM(s0_ctl_recv+ts1)=AX0;
	AX0=0xffff;	DM(s0_ctl_recv+ts2)=AX0;
	AX0=0xffff;	DM(s0_ctl_recv+ts3)=AX0;
{ data time slot }	
	AX0=0x0;	DM(s0_dat_send+ts1)=AX0;
	AX0=0x0;	DM(s0_dat_send+ts2)=AX0;
	AX0=0x0;	DM(s0_dat_send+ts3)=AX0;
	AX0=0x0;	DM(s0_dat_send+ts4)=AX0;
	AX0=0xc0;	DM(s0_dat_send+ts5)=AX0; /* out enb,Rch:0dbATT */
	AX0=0x00;	DM(s0_dat_send+ts6)=AX0; /* Rch:0dbATT */
	AX0=0xc6;	DM(s0_dat_send+ts7)=AX0; /* Line-I,Lch:gain9dB */
	AX0=0xf6;	DM(s0_dat_send+ts8)=AX0; /* Rch:gain9dB */
	AX0=0xaa;	DM(s0_dat_recv+ts1)=AX0;
	AX0=0xaa;	DM(s0_dat_recv+ts2)=AX0;
	AX0=0xaa;	DM(s0_dat_recv+ts3)=AX0;
	AX0=0x0;	DM(s0_dat_recv+ts4)=AX0;
	AX0=0x0;	DM(s0_dat_recv+ts5)=AX0;
	AX0=0x0;	DM(s0_dat_recv+ts6)=AX0;
	AX0=0x0;	DM(s0_dat_recv+ts7)=AX0;
	AX0=0x0;	DM(s0_dat_recv+ts8)=AX0;
{ control mode set }
	I0 =^s0_ctl_send; M0=1; L0=8; 
	I1 =^s0_ctl_recv; M1=1; L1=8; 
	AX0 =DM(I0,M0); TX0=AX0;
	AX0=0x17; 			/* tx=I0,rx=I1 autobuf enable */
	DM(Sport0_Autobuf_Ctrl)=AX0;
	AX0 = 0x1408;	DM(Sys_Ctrl_Reg) = AX0;	/* sport0 enable */
	ifc=0x3f; 				/* all int clr */
	IMASK=0x08;				/* s0 rx int enable */
loop1:	idle;
	CALL control_mode_chk;
	IF NE jump loop1;
	ifc=0x3f; 
	IMASK=0x10;					/* s0 tx int enb */
	AX0=0x0C;	DM(s0_ctl_send+ts1)=AX0;	/* clb set */
	idle;
	idle;
	idle;
	IMASK=0; IFC=0x3F; 			
	AX0=0x00;	DM(Sport0_Autobuf_Ctrl)=AX0;
	AX0=0x0408;	DM(Sys_Ctrl_Reg) = AX0;		/* sport0 disable */
{ dsp set data mode }	
	AX0=0x8607;	DM(Sport0_Ctrl_Reg)=AX0;	/* rfs receive mode */
	AX0=0xff;	DM(Sport0_Tx_Words0)=AX0;	/* 64bit */
	AX0=0xff;	DM(Sport0_Rx_Words0)=AX0;	/* 64bit */
	AX0=0x00;	DM(Sport0_Tx_Words1)=AX0;
	AX0=0x00;	DM(Sport0_Rx_Words1)=AX0;
	I0 =^s0_dat_send; M0=1; L0=8;
	I1 =^s0_dat_recv; M1=1; L1=8;
	I2 =^s0_dat_recv; M2=1; L2=4;
	I3 =^s0_dat_send; M3=1; L3=4;
	AX0 = 0x1408;	DM(Sys_Ctrl_Reg)=AX0;		/* sport0 enable */
	AX0=DM(I0,M0); TX0=AX0;		
	AX0=0x17; 			/* tx=I0,rx=I1 autobuf enable */
	DM(Sport0_Autobuf_Ctrl)=AX0;   
	AX0=dc;		DM(codec_ctrl)=AX0;		/* set dc to high */
	IFC=0x3f; IMASK=0x08;	
loop2:	idle;
	AY1=DM(I2,M2);	DM(I3,M3)=AY1;	/* left  msb 8bit */
	AY1=DM(I2,M2);	DM(I3,M3)=AY1;	/* left  lsb 8bit */
	AY1=DM(I2,M2);	DM(I3,M3)=AY1;	/* right msb 8bit */
	AY1=DM(I2,M2);	DM(I3,M3)=AY1;	/* right msb 8bit */
	jump loop2;
control_mode_chk: 
	AX0=DM(s0_ctl_recv+ts1);
	AY0=0x04; AR=AX0 and AY0;
	IF NE jump chk1;
	AX0=DM(s0_ctl_send+ts2);
	AY0=DM(s0_ctl_recv+ts2);
	AR=AX0-AY0;
	IF NE jump chk1;
	AX0=DM(s0_ctl_send+ts3);
	AY0=DM(s0_ctl_recv+ts3);
	AF=AX0 xor AY0;
	AX0=0xFF7F; AR=AX0 and AF;
chk1:	rts;
s0send:	rti;
s0recv:	rti;

.ENDMOD;

=============================================================================


.MODULE/RAM/BOOT=0/ABS=0 test;

{ SYSTEM I/O ADDRESS DEFINES }
.const  Sys_Ctrl_Reg= 		    0x3fff;
.const  Dm_Wait_Reg= 	            0x3ffe;
.const  Tperiod_Reg=                0x3ffd;
.const  Tcount_Reg=                 0x3ffc;
.const  Tscale_Reg=                 0x3ffb;
.const  Sport0_Rx_Words1=           0x3ffa;
.const  Sport0_Rx_Words0=           0x3ff9;
.const  Sport0_Tx_Words1=           0x3ff8;
.const  Sport0_Tx_Words0=           0x3ff7;
.const  Sport0_Ctrl_Reg=            0x3ff6;
.const  Sport0_Sclkdiv=             0x3ff5;
.const  Sport0_Rfsdiv=              0x3ff4;
.const  Sport0_Autobuf_Ctrl=        0x3ff3;
.const  Sport1_Ctrl_Reg=            0x3ff2;
.const  Sport1_Sclkdiv=             0x3ff1;
.const  Sport1_Rfsdiv=              0x3ff0;
.const  Sport1_Autobuf_Ctrl=        0x3fef;

.CONST comcrdy	= 0x0803;
.CONST comdrdy	= 0x0804;
.CONST cpudt 	= 0x0810;
.CONST dspdt	= 0x0811;

{ BOAD REGISTERS }
.CONST hs_readonly	= 0x0600;
.CONST handshake	= 0x0700;
.CONST dipswitch	= 0x0400;
.CONST codec_ctrl	= 0x0400;

{ CONTROLE BITS }
.CONST d2c	= 0x2000;
.CONST c2d	= 0x1000;
.CONST s8	= 0x8000;
.CONST s4	= 0x4000;
.CONST s2	= 0x2000;
.CONST s1	= 0x1000;
.CONST dc	= 0x1000;
.CONST c2denb	= 0x2000;
.CONST extenb	= 0x4000;

{ MEMORY STRUCTURE }
.CONST	dm_top		= 0x0800;
.CONST	dm_bottom	= 0x3BFF;
.CONST	pm_top		= 0x0000;
.CONST	pm_bottom	= 0x3FFF;

.CONST	ext_dm_top	= 0x0800;
.CONST	ext_dm_bottom	= 0x37FF;
.CONST	int_dm_top	= 0x3800;
.CONST	int_dm_bottom	= 0x3BFF;
.CONST	ext_pm_top	= 0x0800;
.CONST	ext_pm_bottom	= 0x3FFF;
.CONST	int_pm_top	= 0x0000;
.CONST	int_pm_bottom	= 0x07FF;

{ TERMINATE PROGRAM }
.CONST	end_of_prog	= 0x001D;

/******************** Special Macro Defines ********************/
#define data_to_mem(data,memory)	AX0=data; DM(memory)=AX0;
#define data_to_reg(data,register)	AX0=data; DM(register)=AX0;
#define interrupt_disable		IFC=0x3f; IMASK=0x00;
#define interrupt_s0_rx_enable		IFC=0x3f; IMASK=0x08;
#define interrupt_s0_tx_enable		IFC=0x3f; IMASK=0x10;
#define waiting_for_interrupt		idle;
#define direct_tx_port_0(i_reg,m_reg)	AX0=DM(i_reg,m_reg); TX0=AX0;
#define serial_port_0_disable		data_to_reg(0x0408,Sys_Ctrl_Reg)
#define serial_port_0_enable		data_to_reg(0x1408,Sys_Ctrl_Reg)
#define autobuf_port_0_disable		data_to_reg(0x0000,Sport0_Autobuf_Ctrl)
#define autobuf_port_0_enable		data_to_reg(0x0017,Sport0_Autobuf_Ctrl)
.MACRO codec_to_AR_reg_mono;
	SR0=DM(I3,M3); AY0=DM(I3,M3);
	SR=lshift SR0 by 8 (lo); AR=SR0 or AY0;
.ENDMACRO;
.MACRO SR0_reg_to_codec_mono;
	AY0=0xff; AR=SR0 and AY0; SR=lshift SR0 by -8 (lo);
	DM(I2,M2)=SR0; DM(I2,M2)=AR;
.ENDMACRO;

/******************** Buffer Memory Defines ********************/
.VAR/DM/RAM/ABS=0x0900/CIRC	fifo_tx[8];
.VAR/DM/RAM/ABS=0x0910/CIRC	fifo_rx[8];

/******************** Reset Vectors Defines ********************/
jump start;	nop; nop; nop;	{Reset Vector}
	RTI;	nop; nop; nop;	{irq2}
	RTI;	nop; nop; nop;	{sport0 TX}
	RTI;	nop; nop; nop;	{sport0 RX}
	RTI;	nop; nop; nop;	{irq0}
	RTI;	nop; nop; nop;	{irq1}
	RTI;	nop; nop; nop;	{timer}

/******************** Common Subroutines ********************/
codec_initialize:
	call codec_system_init;
	call codec_init_command_mode;
	call codec_init_data_mode;
	rts;
codec_system_init:
	data_to_reg(0x01,Dm_Wait_Reg)		/* 1 wait */
	data_to_reg(0xff,Sport0_Rfsdiv)		/* Multi-ch, 256bit */
	data_to_reg(0x00,Sport0_Sclkdiv)	/* divide rate */
	data_to_reg(0xff,Sport0_Tx_Words0)	/* LSB 16bit Tx */
	data_to_reg(0xff,Sport0_Rx_Words0)	/*           Rx */
	data_to_reg(0x00,Sport0_Tx_Words1)	/* MSB 16bit Tx */
	data_to_reg(0x00,Sport0_Rx_Words1)	/*           Rx */
	rts;
codec_init_command_mode:
	interrupt_disable
	serial_port_0_disable
	autobuf_port_0_disable
	data_to_mem(0x08,fifo_tx+0)	/* olb=1, clb=0(control) */
	data_to_mem(0x1c,fifo_tx+1)	/* 32KHz, Stereo, 16bit */
	data_to_mem(0x9a,fifo_tx+2)	/* 256bit, x1, gen.clk */
	data_to_mem(0x00,fifo_tx+3)	/* (reserved) */
	data_to_mem(0xc0,fifo_tx+4)	/* (reserved) */
	data_to_mem(0x00,fifo_tx+6)	/* (reserved) */
	I0=^fifo_tx; M0=1; L0=8; 
	I1=^fifo_rx; M1=1; L1=8; 
	data_to_reg(0xc707,Sport0_Ctrl_Reg)	/* CODEC --> Setting Mode */
	direct_tx_port_0(I0,M0)
	autobuf_port_0_enable			/* tx=I0, rx=I1 */
	serial_port_0_enable
	interrupt_s0_rx_enable
loop_1:
	waiting_for_interrupt
	call check_1;
	if ne jump loop_1;
	interrupt_s0_tx_enable
	data_to_mem(0x000C,fifo_tx+0)		/* clb set */
	waiting_for_interrupt
	waiting_for_interrupt
	waiting_for_interrupt
	rts;
check_1: 
	AX0=DM(fifo_rx+0); AY0=0x04; AR=AX0 and AY0;
	if ne jump chk_exit;
	AX0=DM(fifo_tx+1); AY0=DM(fifo_rx+1); AR=AX0-AY0;
	if ne jump chk_exit;
	AX0=DM(fifo_tx+2); AY0=DM(fifo_rx+2); AF=AX0 xor AY0;
	AX0=0xFF7F; AR=AX0 and AF;
chk_exit:
	rts;
codec_init_data_mode:
	interrupt_disable
	serial_port_0_disable
	autobuf_port_0_disable
	data_to_mem(0x00,fifo_tx+0)	/* (dummy) */
	data_to_mem(0x00,fifo_tx+1)	/*    |    */
	data_to_mem(0x00,fifo_tx+2)	/*    |    */
	data_to_mem(0x00,fifo_tx+3)	/* (dummy) */
	data_to_mem(0xc0,fifo_tx+4)	/* Output Enable, Lch : 0db ATT */
	data_to_mem(0x00,fifo_tx+5)	/*                Rch : 0db ATT */
	data_to_mem(0xc6,fifo_tx+6)	/* Input <- Line, Lch : gain 9dB */
	data_to_mem(0xf6,fifo_tx+7)	/*                Rch : gain 9dB */
	I0=^fifo_tx; M0=1; L0=8;
	I1=^fifo_rx; M1=1; L1=8;
	I2=^fifo_tx; M2=1; L2=2;		/* Data Buffer for Tx (L) */
	I3=^fifo_rx; M3=1; L3=2;		/*                 Rx (L) */
	data_to_reg(0x8607,Sport0_Ctrl_Reg)	/* CODEC --> Running Mode */
	data_to_reg(dc,codec_ctrl)		/* Change to Data Mode */
	direct_tx_port_0(I0,M0)
	autobuf_port_0_enable			/* tx=I0, rx=I1 */
	serial_port_0_enable
	interrupt_s0_rx_enable
	rts;

.VAR/DM/RAM/ABS=0x0800		interface;
.VAR/DM/RAM/ABS=0x2000/CIRC	data_fifo[4096];

start:
	call codec_initialize;		/* DSP_HEAD.H */
	I4=^data_fifo; M4=1; L4=4096;
	data_to_mem(1024,interface)
	I5=^data_fifo; M5=1; L5=0;
main:
	codec_to_AR_reg_mono;		/* Get A/D Data : DSP_HEAD.H */

	DM(I4,M4)=AR;
	DM(interface+1)=AR;

	AX0=DM(interface);
	AY0=I4;
	AR=AX0+AY0;
	AY0=0x2fff;
	AR=AR and AY0;
	I5=AR;
	SR0=DM(I5,M5);
	DM(interface+2)=SR0;

	SR0_reg_to_codec_mono;		/* Put to D/A : DSP_HEAD.H */
	waiting_for_interrupt
	jump main;

.ENDMOD;

=============================================================================


.MODULE/RAM/BOOT=0/ABS=0 test;

{ SYSTEM I/O ADDRESS DEFINES }
.const  Sys_Ctrl_Reg= 		    0x3fff;
.const  Dm_Wait_Reg= 	            0x3ffe;
.const  Tperiod_Reg=                0x3ffd;
.const  Tcount_Reg=                 0x3ffc;
.const  Tscale_Reg=                 0x3ffb;
.const  Sport0_Rx_Words1=           0x3ffa;
.const  Sport0_Rx_Words0=           0x3ff9;
.const  Sport0_Tx_Words1=           0x3ff8;
.const  Sport0_Tx_Words0=           0x3ff7;
.const  Sport0_Ctrl_Reg=            0x3ff6;
.const  Sport0_Sclkdiv=             0x3ff5;
.const  Sport0_Rfsdiv=              0x3ff4;
.const  Sport0_Autobuf_Ctrl=        0x3ff3;
.const  Sport1_Ctrl_Reg=            0x3ff2;
.const  Sport1_Sclkdiv=             0x3ff1;
.const  Sport1_Rfsdiv=              0x3ff0;
.const  Sport1_Autobuf_Ctrl=        0x3fef;

.CONST comcrdy	= 0x0803;
.CONST comdrdy	= 0x0804;
.CONST cpudt 	= 0x0810;
.CONST dspdt	= 0x0811;

{ BOAD REGISTERS }
.CONST hs_readonly	= 0x0600;
.CONST handshake	= 0x0700;
.CONST dipswitch	= 0x0400;
.CONST codec_ctrl	= 0x0400;

{ CONTROLE BITS }
.CONST d2c	= 0x2000;
.CONST c2d	= 0x1000;
.CONST s8	= 0x8000;
.CONST s4	= 0x4000;
.CONST s2	= 0x2000;
.CONST s1	= 0x1000;
.CONST dc	= 0x1000;
.CONST c2denb	= 0x2000;
.CONST extenb	= 0x4000;

{ MEMORY STRUCTURE }
.CONST	dm_top		= 0x0800;
.CONST	dm_bottom	= 0x3BFF;
.CONST	pm_top		= 0x0000;
.CONST	pm_bottom	= 0x3FFF;

.CONST	ext_dm_top	= 0x0800;
.CONST	ext_dm_bottom	= 0x37FF;
.CONST	int_dm_top	= 0x3800;
.CONST	int_dm_bottom	= 0x3BFF;
.CONST	ext_pm_top	= 0x0800;
.CONST	ext_pm_bottom	= 0x3FFF;
.CONST	int_pm_top	= 0x0000;
.CONST	int_pm_bottom	= 0x07FF;

{ TERMINATE PROGRAM }
.CONST	end_of_prog	= 0x001D;

/******************** Special Macro Defines ********************/
#define data_to_mem(data,memory)	AX0=data; DM(memory)=AX0;
#define data_to_reg(data,register)	AX0=data; DM(register)=AX0;
#define interrupt_disable		IFC=0x3f; IMASK=0x00;
#define interrupt_s0_rx_enable		IFC=0x3f; IMASK=0x08;
#define interrupt_s0_tx_enable		IFC=0x3f; IMASK=0x10;
#define waiting_for_interrupt		idle;
#define direct_tx_port_0(i_reg,m_reg)	AX0=DM(i_reg,m_reg); TX0=AX0;
#define serial_port_0_disable		data_to_reg(0x0408,Sys_Ctrl_Reg)
#define serial_port_0_enable		data_to_reg(0x1408,Sys_Ctrl_Reg)
#define autobuf_port_0_disable		data_to_reg(0x0000,Sport0_Autobuf_Ctrl)
#define autobuf_port_0_enable		data_to_reg(0x0017,Sport0_Autobuf_Ctrl)
.MACRO codec_to_AR_reg_mono;
	SR0=DM(I3,M3); AY0=DM(I3,M3);
	SR=lshift SR0 by 8 (lo); AR=SR0 or AY0;
.ENDMACRO;
.MACRO SR0_reg_to_codec_mono;
	AY0=0xff; AR=SR0 and AY0; SR=lshift SR0 by -8 (lo);
	DM(I2,M2)=SR0; DM(I2,M2)=AR;
.ENDMACRO;

/******************** Buffer Memory Defines ********************/
.VAR/DM/RAM/ABS=0x0900/CIRC	fifo_tx[8];
.VAR/DM/RAM/ABS=0x0910/CIRC	fifo_rx[8];

/******************** Reset Vectors Defines ********************/
jump start;	nop; nop; nop;	{Reset Vector}
	RTI;	nop; nop; nop;	{irq2}
	RTI;	nop; nop; nop;	{sport0 TX}
	RTI;	nop; nop; nop;	{sport0 RX}
	RTI;	nop; nop; nop;	{irq0}
	RTI;	nop; nop; nop;	{irq1}
	RTI;	nop; nop; nop;	{timer}

/******************** Common Subroutines ********************/
codec_initialize:
	call codec_system_init;
	call codec_init_command_mode;
	call codec_init_data_mode;
	rts;
codec_system_init:
	data_to_reg(0x01,Dm_Wait_Reg)		/* 1 wait */
	data_to_reg(0xff,Sport0_Rfsdiv)		/* Multi-ch, 256bit */
	data_to_reg(0x00,Sport0_Sclkdiv)	/* divide rate */
	data_to_reg(0xff,Sport0_Tx_Words0)	/* LSB 16bit Tx */
	data_to_reg(0xff,Sport0_Rx_Words0)	/*           Rx */
	data_to_reg(0x00,Sport0_Tx_Words1)	/* MSB 16bit Tx */
	data_to_reg(0x00,Sport0_Rx_Words1)	/*           Rx */
	rts;
codec_init_command_mode:
	interrupt_disable
	serial_port_0_disable
	autobuf_port_0_disable
	data_to_mem(0x08,fifo_tx+0)	/* olb=1, clb=0(control) */
	data_to_mem(0x1c,fifo_tx+1)	/* 32KHz, Stereo, 16bit */
	data_to_mem(0x9a,fifo_tx+2)	/* 256bit, x1, gen.clk */
	data_to_mem(0x00,fifo_tx+3)	/* (reserved) */
	data_to_mem(0xc0,fifo_tx+4)	/* (reserved) */
	data_to_mem(0x00,fifo_tx+6)	/* (reserved) */
	I0=^fifo_tx; M0=1; L0=8; 
	I1=^fifo_rx; M1=1; L1=8; 
	data_to_reg(0xc707,Sport0_Ctrl_Reg)	/* CODEC --> Setting Mode */
	direct_tx_port_0(I0,M0)
	autobuf_port_0_enable			/* tx=I0, rx=I1 */
	serial_port_0_enable
	interrupt_s0_rx_enable
loop_1:
	waiting_for_interrupt
	call check_1;
	if ne jump loop_1;
	interrupt_s0_tx_enable
	data_to_mem(0x000C,fifo_tx+0)		/* clb set */
	waiting_for_interrupt
	waiting_for_interrupt
	waiting_for_interrupt
	rts;
check_1: 
	AX0=DM(fifo_rx+0); AY0=0x04; AR=AX0 and AY0;
	if ne jump chk_exit;
	AX0=DM(fifo_tx+1); AY0=DM(fifo_rx+1); AR=AX0-AY0;
	if ne jump chk_exit;
	AX0=DM(fifo_tx+2); AY0=DM(fifo_rx+2); AF=AX0 xor AY0;
	AX0=0xFF7F; AR=AX0 and AF;
chk_exit:
	rts;
codec_init_data_mode:
	interrupt_disable
	serial_port_0_disable
	autobuf_port_0_disable
	data_to_mem(0x00,fifo_tx+0)	/* (dummy) */
	data_to_mem(0x00,fifo_tx+1)	/*    |    */
	data_to_mem(0x00,fifo_tx+2)	/*    |    */
	data_to_mem(0x00,fifo_tx+3)	/* (dummy) */
	data_to_mem(0xc0,fifo_tx+4)	/* Output Enable, Lch : 0db ATT */
	data_to_mem(0x00,fifo_tx+5)	/*                Rch : 0db ATT */
	data_to_mem(0xc6,fifo_tx+6)	/* Input <- Line, Lch : gain 9dB */
	data_to_mem(0xf6,fifo_tx+7)	/*                Rch : gain 9dB */
	I0=^fifo_tx; M0=1; L0=8;
	I1=^fifo_rx; M1=1; L1=8;
	I2=^fifo_tx; M2=1; L2=2;		/* Data Buffer for Tx (L) */
	I3=^fifo_rx; M3=1; L3=2;		/*                 Rx (L) */
	data_to_reg(0x8607,Sport0_Ctrl_Reg)	/* CODEC --> Running Mode */
	data_to_reg(dc,codec_ctrl)		/* Change to Data Mode */
	direct_tx_port_0(I0,M0)
	autobuf_port_0_enable			/* tx=I0, rx=I1 */
	serial_port_0_enable
	interrupt_s0_rx_enable
	rts;

.VAR/DM/RAM/ABS=0x0800		interface;
.VAR/DM/RAM/ABS=0x2000/CIRC	data_fifo[4096];

start:
	call codec_initialize;
	I4=^data_fifo; M4=1; L4=4096;
	data_to_mem(1024,interface)
	I5=^data_fifo; M5=1; L5=0;
main:
	call codec_to_Y_reg_mono;
	DM(I4,M4)=AY0;		/* Left  */

	AX0=DM(interface);
	AY0=I4;
	AR=AX0+AY0;
	AY0=0x2fff;
	AR=AR and AY0;
	I5=AR;
	AY0=DM(I5,M5);

	call Y_reg_to_codec_mono;
	waiting_for_interrupt
	jump main;

codec_to_Y_reg_mono:
	SR0=DM(I3,M3);			/* Left  MSB 8bit */
	AY0=DM(I3,M3);			/*       LSB 8bit */
	SR=lshift SR0 by 8 (lo);
	AR=SR0 or AY0;
	AY0=AR;
	rts;

Y_reg_to_codec_mono:
	AX0=0xff;
	SR0=AY0;
	SR=lshift SR0 by -8 (lo);
	AR=AX0 and AY0;
	DM(I2,M2)=SR0;			/* Left  MSB 8bit */
	DM(I2,M2)=AR;			/*       LSB 8bit */
	rts;

.ENDMOD;

=============================================================================


.MODULE/RAM/BOOT=0/ABS=0 test;

{ SYSTEM I/O ADDRESS DEFINES }
.const  Sys_Ctrl_Reg= 		    0x3fff;
.const  Dm_Wait_Reg= 	            0x3ffe;
.const  Tperiod_Reg=                0x3ffd;
.const  Tcount_Reg=                 0x3ffc;
.const  Tscale_Reg=                 0x3ffb;
.const  Sport0_Rx_Words1=           0x3ffa;
.const  Sport0_Rx_Words0=           0x3ff9;
.const  Sport0_Tx_Words1=           0x3ff8;
.const  Sport0_Tx_Words0=           0x3ff7;
.const  Sport0_Ctrl_Reg=            0x3ff6;
.const  Sport0_Sclkdiv=             0x3ff5;
.const  Sport0_Rfsdiv=              0x3ff4;
.const  Sport0_Autobuf_Ctrl=        0x3ff3;
.const  Sport1_Ctrl_Reg=            0x3ff2;
.const  Sport1_Sclkdiv=             0x3ff1;
.const  Sport1_Rfsdiv=              0x3ff0;
.const  Sport1_Autobuf_Ctrl=        0x3fef;

.CONST comcrdy	= 0x0803;
.CONST comdrdy	= 0x0804;
.CONST cpudt 	= 0x0810;
.CONST dspdt	= 0x0811;

{ BOAD REGISTERS }
.CONST hs_readonly	= 0x0600;
.CONST handshake	= 0x0700;
.CONST dipswitch	= 0x0400;
.CONST codec_ctrl	= 0x0400;

{ CONTROLE BITS }
.CONST d2c	= 0x2000;
.CONST c2d	= 0x1000;
.CONST s8	= 0x8000;
.CONST s4	= 0x4000;
.CONST s2	= 0x2000;
.CONST s1	= 0x1000;
.CONST dc	= 0x1000;
.CONST c2denb	= 0x2000;
.CONST extenb	= 0x4000;

{ MEMORY STRUCTURE }
.CONST	dm_top		= 0x0800;
.CONST	dm_bottom	= 0x3BFF;
.CONST	pm_top		= 0x0000;
.CONST	pm_bottom	= 0x3FFF;

.CONST	ext_dm_top	= 0x0800;
.CONST	ext_dm_bottom	= 0x37FF;
.CONST	int_dm_top	= 0x3800;
.CONST	int_dm_bottom	= 0x3BFF;
.CONST	ext_pm_top	= 0x0800;
.CONST	ext_pm_bottom	= 0x3FFF;
.CONST	int_pm_top	= 0x0000;
.CONST	int_pm_bottom	= 0x07FF;

{ TERMINATE PROGRAM }
.CONST	end_of_prog	= 0x001D;

/******************** Special Macro Defines ********************/
#define data_to_mem(data,memory)	AX0=data; DM(memory)=AX0;
#define data_to_reg(data,register)	AX0=data; DM(register)=AX0;
#define interrupt_disable		IFC=0x3f; IMASK=0x00;
#define interrupt_s0_rx_enable		IFC=0x3f; IMASK=0x08;
#define interrupt_s0_tx_enable		IFC=0x3f; IMASK=0x10;
#define waiting_for_interrupt		idle;
#define direct_tx_port_0(i_reg,m_reg)	AX0=DM(i_reg,m_reg); TX0=AX0;
#define serial_port_0_disable		data_to_reg(0x0408,Sys_Ctrl_Reg)
#define serial_port_0_enable		data_to_reg(0x1408,Sys_Ctrl_Reg)
#define autobuf_port_0_disable		data_to_reg(0x0000,Sport0_Autobuf_Ctrl)
#define autobuf_port_0_enable		data_to_reg(0x0017,Sport0_Autobuf_Ctrl)
.MACRO codec_to_AR_reg_mono;
	SR0=DM(I3,M3); AY0=DM(I3,M3);
	SR=lshift SR0 by 8 (lo); AR=SR0 or AY0;
.ENDMACRO;
.MACRO SR0_reg_to_codec_mono;
	AY0=0xff; AR=SR0 and AY0; SR=lshift SR0 by -8 (lo);
	DM(I2,M2)=SR0; DM(I2,M2)=AR;
.ENDMACRO;

/******************** Buffer Memory Defines ********************/
.VAR/DM/RAM/ABS=0x0900/CIRC	fifo_tx[8];
.VAR/DM/RAM/ABS=0x0910/CIRC	fifo_rx[8];

/******************** Reset Vectors Defines ********************/
jump start;	nop; nop; nop;	{Reset Vector}
	RTI;	nop; nop; nop;	{irq2}
	RTI;	nop; nop; nop;	{sport0 TX}
	RTI;	nop; nop; nop;	{sport0 RX}
	RTI;	nop; nop; nop;	{irq0}
	RTI;	nop; nop; nop;	{irq1}
	RTI;	nop; nop; nop;	{timer}

/******************** Common Subroutines ********************/
codec_initialize:
	call codec_system_init;
	call codec_init_command_mode;
	call codec_init_data_mode;
	rts;
codec_system_init:
	data_to_reg(0x01,Dm_Wait_Reg)		/* 1 wait */
	data_to_reg(0xff,Sport0_Rfsdiv)		/* Multi-ch, 256bit */
	data_to_reg(0x00,Sport0_Sclkdiv)	/* divide rate */
	data_to_reg(0xff,Sport0_Tx_Words0)	/* LSB 16bit Tx */
	data_to_reg(0xff,Sport0_Rx_Words0)	/*           Rx */
	data_to_reg(0x00,Sport0_Tx_Words1)	/* MSB 16bit Tx */
	data_to_reg(0x00,Sport0_Rx_Words1)	/*           Rx */
	rts;
codec_init_command_mode:
	interrupt_disable
	serial_port_0_disable
	autobuf_port_0_disable
	data_to_mem(0x08,fifo_tx+0)	/* olb=1, clb=0(control) */
	data_to_mem(0x1c,fifo_tx+1)	/* 32KHz, Stereo, 16bit */
	data_to_mem(0x9a,fifo_tx+2)	/* 256bit, x1, gen.clk */
	data_to_mem(0x00,fifo_tx+3)	/* (reserved) */
	data_to_mem(0xc0,fifo_tx+4)	/* (reserved) */
	data_to_mem(0x00,fifo_tx+6)	/* (reserved) */
	I0=^fifo_tx; M0=1; L0=8; 
	I1=^fifo_rx; M1=1; L1=8; 
	data_to_reg(0xc707,Sport0_Ctrl_Reg)	/* CODEC --> Setting Mode */
	direct_tx_port_0(I0,M0)
	autobuf_port_0_enable			/* tx=I0, rx=I1 */
	serial_port_0_enable
	interrupt_s0_rx_enable
loop_1:
	waiting_for_interrupt
	call check_1;
	if ne jump loop_1;
	interrupt_s0_tx_enable
	data_to_mem(0x000C,fifo_tx+0)		/* clb set */
	waiting_for_interrupt
	waiting_for_interrupt
	waiting_for_interrupt
	rts;
check_1: 
	AX0=DM(fifo_rx+0); AY0=0x04; AR=AX0 and AY0;
	if ne jump chk_exit;
	AX0=DM(fifo_tx+1); AY0=DM(fifo_rx+1); AR=AX0-AY0;
	if ne jump chk_exit;
	AX0=DM(fifo_tx+2); AY0=DM(fifo_rx+2); AF=AX0 xor AY0;
	AX0=0xFF7F; AR=AX0 and AF;
chk_exit:
	rts;
codec_init_data_mode:
	interrupt_disable
	serial_port_0_disable
	autobuf_port_0_disable
	data_to_mem(0x00,fifo_tx+0)	/* (dummy) */
	data_to_mem(0x00,fifo_tx+1)	/*    |    */
	data_to_mem(0x00,fifo_tx+2)	/*    |    */
	data_to_mem(0x00,fifo_tx+3)	/* (dummy) */
	data_to_mem(0xc0,fifo_tx+4)	/* Output Enable, Lch : 0db ATT */
	data_to_mem(0x00,fifo_tx+5)	/*                Rch : 0db ATT */
	data_to_mem(0xc6,fifo_tx+6)	/* Input <- Line, Lch : gain 9dB */
	data_to_mem(0xf6,fifo_tx+7)	/*                Rch : gain 9dB */
	I0=^fifo_tx; M0=1; L0=8;
	I1=^fifo_rx; M1=1; L1=8;
	I2=^fifo_tx; M2=1; L2=2;		/* Data Buffer for Tx (L) */
	I3=^fifo_rx; M3=1; L3=2;		/*                 Rx (L) */
	data_to_reg(0x8607,Sport0_Ctrl_Reg)	/* CODEC --> Running Mode */
	data_to_reg(dc,codec_ctrl)		/* Change to Data Mode */
	direct_tx_port_0(I0,M0)
	autobuf_port_0_enable			/* tx=I0, rx=I1 */
	serial_port_0_enable
	interrupt_s0_rx_enable
	rts;

.VAR/DM/RAM/ABS=0x3820		buffer[16];
.VAR/DM/RAM/ABS=0x0800		interface[16];
.VAR/DM/RAM/ABS=0x1000/CIRC	data_fifo_l[2048];
.VAR/DM/RAM/ABS=0x2000/CIRC	data_fifo_r[2048];

start:
	call codec_initialize;
	I4=^data_fifo_l; M4=1; L4=2048; 
	I5=^data_fifo_r; M5=1; L5=2048; 
	data_to_mem(1024,interface+0)
	data_to_mem(1024,interface+1)
	I6=^data_fifo_l+1024; M6=1; L6=0; 
	I7=^data_fifo_r+1024; M7=1; L7=0; 
main:
	call codec_to_Y_reg;
	DM(I4,M4)=AY0;		/* Left  */
	DM(I5,M5)=AY1;		/* Right */
	SR0=AY0;
	SR=ashift SR0 by -1 (lo);
	DM(buffer+0)=SR0;
	SR0=AY1;
	SR=ashift SR0 by -1 (lo);
	DM(buffer+1)=SR0;

jump dummy;

	AX0=DM(interface+0);
	AY0=I4;
	AR=AX0+AY0;
	AY0=0x17ff;
	AR=AR and AY0;
	I6=AR;
	SR0=DM(I6,M6);
	SR=ashift SR0 by -1 (lo);
	AX0=SR0;
	AX1=DM(interface+1);
	AY1=I5;
	AR=AX1+AY1;
	AY1=0x17ff;
	AR=AR and AY1;
	I7=AR;
	SR0=DM(I7,M7);
	SR=ashift SR0 by -1 (lo);
	AX1=SR0;

	AY0=DM(buffer+0);
	AR=AX0+AY0;
	AY0=AR;
	AY1=DM(buffer+1);
	AR=AX1+AY1;
	AY1=AR;

dummy:

	call Y_reg_to_codec;
	waiting_for_interrupt
	jump main;

codec_to_Y_reg:
	SR0=DM(I3,M3);			/* Left  MSB 8bit */
	AY0=DM(I3,M3);			/*       LSB 8bit */
	SR=lshift SR0 by 8 (lo);
	AR=SR0 or AY0;
	AY0=AR;
	SR0=DM(I3,M3);			/* Right MSB 8bit */
	AY1=DM(I3,M3);			/*       LSB 8bit */
	SR=lshift SR0 by 8 (lo);
	AR=SR0 or AY1;
	AY1=AR;
	rts;

Y_reg_to_codec:
	AX0=0xff;
	SR0=AY0;
	SR=lshift SR0 by -8 (lo);
	AR=AX0 and AY0;
	DM(I2,M2)=SR0;			/* Left  MSB 8bit */
	DM(I2,M2)=AR;			/*       LSB 8bit */
	SR0=AY1;
	SR=lshift SR0 by -8 (lo);
	AR=AX0 and AY1;
	DM(I2,M2)=SR0;			/* Right MSB 8bit */
	DM(I2,M2)=AR;			/*       LSB 8bit */
	rts;

.ENDMOD;