LIST 39

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;##### RAM Map #####
	dseg
	org	0000h
rx_fifo_0	ds	4096
rx_fifo_1	ds	4096
rx_fifo_2	ds	4096
rx_fifo_3	ds	4096
tx_fifo		ds	8192
rx_top_0	ds	2
rx_end_0	ds	2
rx_top_1	ds	2
rx_end_1	ds	2
rx_top_2	ds	2
rx_end_2	ds	2
rx_top_3	ds	2
rx_end_3	ds	2
tx_top		ds	2
tx_end		ds	2
rx_data		ds	4
rsb		ds	4
dcb		ds	4
channel		ds	4
keyno		ds	4

;##### I/O Map #####
	cseg
uart_0		equ	0080h
uart_1		equ	0082h
uart_2		equ	0084h
uart_3		equ	0086h

;##### MACRO #####
all_out	macro	@1
	ld	a,@1
	out	(uart_0+1),a
	out	(uart_1+1),a
	out	(uart_2+1),a
	out	(uart_3+1),a
	endm
rx_set	macro	@1,@2,@3
	ld	de,(@3)
	ld	a,@1
	or	d
	ld	h,a
	ld	l,e
	in	a,(@2+0)
	ld	(hl),a
	inc	de
	res	4,d
	ld	(@3),de
	ret
	endm
rx_chk	macro	@1,@2,@3,@4
	ld	de,(@2)
	ld	hl,(@1)
	and	a			; CY <-- 0
	sbc	hl,de
	ret	z
	ld	a,@3
	or	d
	ld	h,a
	ld	l,e
	ld	b,(hl)			; [B] = Rx Data
	inc	de
	res	4,d
	ld	(@2),de
	bit	7,b
	jr	z,50$			; running
	ld	a,b
	cp	0f8h
	ret	nc
	cp	0f0h
	jr	c,10$
	xor	a
	ld	(rsb+@4),a
	ret
10$:
	ld	a,b
	and	00001111b
	ld	(channel+@4),a
	ld	a,b
	and	11110000b
	ld	(rsb+@4),a
	xor	a
	ld	(dcb+@4),a
	ret
50$:
	ld	a,(rsb+@4)
	cp	0
	ret	z
	cp	0c0h
	jr	z,70$
	cp	0d0h
	jr	z,70$
	ld	a,(dcb+@4)
	cp	0
	jr	nz,90$
	inc	a
	ld	(dcb+@4),a
	ld	a,b
	ld	(keyno+@4),a
	ret
70$:
	ld	c,b
	ld	a,(rsb+@4)
	ld	d,a
	ld	a,(channel+@4)
	or	d
	ld	b,a
	call	tx_fifo_set
	ld	b,c
	call	tx_fifo_set
	ret
90$:
	xor	a
	ld	(dcb+@4),a
	ld	c,b
	ld	a,(rsb+@4)
	ld	d,a
	ld	a,(channel+@4)
	or	d
	ld	b,a
	call	tx_fifo_set
	ld	a,(keyno+@4)
	ld	b,a
	call	tx_fifo_set
	ld	b,c
	call	tx_fifo_set
	ret
	endm

;##### RESET #####
	org	0000h
	ld      sp,0ffffh
	di
	im      1
	call    initialize
	ei
	jp      loop

;##### INT / NMI #####
	org     0038h
	ex	af,af'
	exx
	call	int_sequence
	exx
	ex	af,af'
	ei
	reti
	org     0066h
	ei
	retn
int_sequence:
	in	a,(uart_0+1)
	bit	1,a
	jr	z,_next_1
	rx_set	10000000b,uart_0,rx_top_0
_next_1:
	in	a,(uart_1+1)
	bit	1,a
	jr	z,_next_2
	rx_set	10010000b,uart_1,rx_top_1
_next_2:
	in	a,(uart_2+1)
	bit	1,a
	jr	z,_next_3
	rx_set	10100000b,uart_2,rx_top_2
_next_3:
	in	a,(uart_3+1)
	bit	1,a
	ret	z
	rx_set	10110000b,uart_3,rx_top_3

;##### MIDI Transmit Data Set : Input=[B] #####
tx_fifo_set:
	ld	de,(tx_top)
	ld	a,11000000b
	or	d
	ld	h,a
	ld	l,e
	ld	(hl),b
	inc	de
	res	5,d
	ld	(tx_top),de
	ret

;##### MIDI Transmit Check #####
tx_fifo_check:
	in	a,(uart_0+1)
	bit	0,a
	ret	z
	ld	de,(tx_end)
	ld	hl,(tx_top)
	and	a			; CY <-- 0
	sbc	hl,de
	ret	z
	ld	a,11000000b
	or	d
	ld	h,a
	ld	l,e
	ld	a,(hl)
	out	(uart_0+0),a
	inc	de
	res	5,d
	ld	(tx_end),de
	ret

;##### MIDI Receive Check #####
rx_fifo_0_check:
	rx_chk	rx_top_0,rx_end_0,10000000b,0
rx_fifo_1_check:
	rx_chk	rx_top_1,rx_end_1,10010000b,1
rx_fifo_2_check:
	rx_chk	rx_top_2,rx_end_2,10100000b,2
rx_fifo_3_check:
	rx_chk	rx_top_3,rx_end_3,10110000b,3

;##### Program #####
loop:
	call	tx_fifo_check
	call	rx_fifo_0_check
	call	tx_fifo_check
	call	rx_fifo_1_check
	call	tx_fifo_check
	call	rx_fifo_2_check
	call	tx_fifo_check
	call	rx_fifo_3_check
	jr	loop

;##### INITIALIZE #####
initialize:
	all_out	0
	all_out	0
	all_out	0
	ld      hl,0e000h
	ld      a,0e8h
_ram_clear_loop:
	ld      (hl),0
	inc     hl
	cp      h
	jr	nc,_ram_clear_loop
	all_out	01000000b
	all_out	01001110b
	all_out	00000101b
	ld	a,0fch
	out	(uart_0+0),a
	ret

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