LIST 38

============================================================================

;##### RAM Map #####
	dseg
	org	0000h
rx_fifo		ds	2048
tx_fifo		ds	2048
rx_top		ds	2
rx_end		ds	2
tx_top		ds	2
tx_end		ds	2
rsb		ds	1
dcb		ds	1
channel		ds	1
keyno		ds	1
timer_flag	ds	1
timer		ds	1
dac_no		ds	1
dac_status	ds	32	; on=[0-254] , off=[255]
sel_4051	ds	1
ad_no		ds	1
ad_comm		ds	1
ad_status	ds	32	; off=[0] , on=[1] , converting=[2]
ad_old		ds	32
eoc_mask	ds	1
threshold	ds	1
outstatus	ds	1
led_mode	ds	1
led_ch		ds	1
led_data	ds	1
led_phase	ds	2

;##### I/O Map #####
	cseg
ctc_0		equ	0010h
sio_a		equ	0018h
sio_b		equ	001ah
pio_a		equ	001ch
pio_b		equ	001eh

;##### MACRO #####
io_set	macro	@1,@2
	ld	a,@2
	out	(@1+1),a
	endm
io_put	macro	@1,@2
	ld	a,@2
	out	(@1+0),a
	endm
dtra_lp	macro
	io_set	sio_a,00000101b		; Resister Point = 5
	io_set	sio_a,11101000b		; Transmit Start, DTR = Low
	io_set	sio_a,00000101b		; Resister Point = 5
	io_set	sio_a,01101000b		; Transmit Start, DTR = High
	endm
dtrb_lp	macro
	io_set	sio_b,00000101b		; Resister Point = 5
	io_set	sio_b,11100000b		; Transmit Disable, DTR = Low
	io_set	sio_b,00000101b		; Resister Point = 5
	io_set	sio_b,01100000b		; Transmit Disable, DTR = High
	endm
pb_set	macro	@1
	out	(pio_b),a
	dtra_lp
	ld	a,11111111b
	res	@1,a
	out	(pio_b),a
	dtrb_lp
	ld	a,11111111b
	out	(pio_b),a
	dtrb_lp
	endm
pb_init	macro
	xor	a
	pb_set	0
	xor	a
	pb_set	1
	xor	a
	pb_set	2
	xor	a
	pb_set	3
	endm
led_out	macro
	ld	a,(led_data)
	xor	0ffh
	pb_set	4
	endm
led_set	macro
	ld	a,(led_mode)
	rrca
	rrca
	rrca
	and	11100000b
	ld	b,a
	ld	a,(led_ch)
	and	00011111b
	or	b
	xor	0ffh
	pb_set	5
	endm
dac_out	macro
	pb_set	6			; input = [A]
	endm
latch_7	macro
	ld	a,(sel_4051)
	pb_set	7
	endm

;##### RESET #####
	org	0000h
	ld      sp,09fffh
	di
	jp      main

;##### INT / NMI #####
	org     0020h
	dw	_midi_
_midi_:
	ex	af,af'
	exx
	ld	de,(rx_top)
	ld	a,10000000b
	or	d
	ld	h,a
	ld	l,e
	in	a,(sio_a+0)
	ld	(hl),a
	inc	de
	res	3,d
	ld	(rx_top),de
	exx
	ex	af,af'
	ei
	reti
	org     0066h
	retn
	org     0070h
	dw	_timer_
_timer_:
	ex	af,af'
	ld	a,1
	ld	(timer_flag),a
	ex	af,af'
	ei
	reti

;##### Main #####
	org	0100h
main:
	ld      hl,08000h
	ld      a,09fh
_ram_clear_loop:
	ld      (hl),0
	inc     hl
	cp      h
	jr	nc,_ram_clear_loop
	io_set	pio_a,0cfh		; Mode 3
	io_set	pio_a,11111111b		; 0:Out / 1:In
	io_set	pio_a,007h		; Interrupt Disable
	io_set	pio_b,0cfh		; Mode 3
	io_set	pio_b,00000000b		; 0:Out / 1:In
	io_set	pio_b,007h		; Interrupt Disable
	io_put	ctc_0,70h		; Int. Address
	io_put	ctc_0,10100101b		; Timer Mode
	io_put	ctc_0,157		; about 10msec
	io_set	sio_b,00011000b		; Channel Reset B
	io_set	sio_b,00000100b		; Resister Point = 4
	io_set	sio_b,11000100b		; Mode
	io_set	sio_b,00000001b		; Resister Point = 1
	io_set	sio_b,00000000b		; Interrupt Mode
	io_set	sio_b,00000101b		; Resister Point = 5
	io_set	sio_b,01100000b		; Transmit Disable, DTR = High
	io_set	sio_b,00000010b		; Resister Point = 2
	io_set	sio_b,20h		; Vector Address
	io_set	sio_a,00011000b		; Channel Reset A
	io_set	sio_a,00000100b		; Resister Point = 4
	io_set	sio_a,11000100b		; Mode
	io_set	sio_a,00000001b		; Resister Point = 1
	io_set	sio_a,00010000b		; Interrupt Mode
	io_set	sio_a,00000101b		; Resister Point = 5
	io_set	sio_a,01101000b		; Transmit Start, DTR = High
	io_set	sio_a,00000011b		; Resister Point = 3
	io_set	sio_a,11000001b		; Receive Start
	nop
	latch_7				; Latch 7 normal waiting
	pb_init
	ld	b,32
lp_001:
	push	bc
	call	dac_off			; all DAC off
	pop	bc
	djnz	lp_001
	led_out				; Data LED 8bit
	led_set				; Mode/Channel LED 3+5bit
	ld	a,4
	ld	(threshold),a
	ld	a,0a0h
	ld	(outstatus),a
	ld	a,00000001b
	ld	(led_phase+0),a
	xor	a
	ld	(led_phase+1),a
	im	2
	ei
	in	a,(sio_a+0)		; dummy read
loop:
	call	rx_data_check
	call	tx_data_check
	call	dac_trans		; DAC data re-new
	call	ad_convert
	jr	loop

;##### Timer Subroutines #####
timer_check:
	ld	a,(timer_flag)
	cp	0
	ret	z
	xor	a
	ld	(timer_flag),a
	ld	a,(timer)
	inc	a
	ld	(timer),a
	cp	100			; about 1sec demo scan
	ret	c
	xor	a
	ld	(timer),a
	ld	a,(led_phase+0)
	cp	00000001b
	jp	z,_timer_001
	cp	00000010b
	jp	z,_timer_010
	cp	00000100b
	jp	z,_timer_100
	ld	a,00000001b
	ld	(led_phase+0),a
	xor	a
	ld	(led_phase+1),a
	ret
_timer_001:
	ld	(led_mode),a
	ld	a,(led_phase+1)
	ld	(led_ch),a
	ld	c,a
	ld	b,0
	ld	hl,ad_status
	add	hl,bc
	ld	a,(hl)
	ld	(led_data),a
	xor	a
	ld	(timer),a
	led_set
	led_out
	ld	a,(led_phase+1)
	inc	a
	ld	(led_phase+1),a
	bit	5,a
	ret	z
	ld	a,00000010b
	ld	(led_phase+0),a
	ld	a,00000001b
	ld	(led_phase+1),a
	ret
_timer_010:
	ld	(led_mode),a
	ld	a,(led_phase+1)
	ld	(led_ch),a
	cp	00010000b
	jr	nz,_timer_010_status
	ld	a,(threshold)
	jr	_timer_010_threshold
_timer_010_status:
	ld	a,(outstatus)
_timer_010_threshold:
	ld	(led_data),a
	xor	a
	ld	(timer),a
	led_set
	led_out
	ld	a,(led_phase+1)
	sla	a
	ld	(led_phase+1),a
	bit	5,a
	ret	z
	ld	a,00000100b
	ld	(led_phase+0),a
	xor	a
	ld	(led_phase+1),a
	ret
_timer_100:
	ld	(led_mode),a
	ld	a,(led_phase+1)
	ld	(led_ch),a
	ld	c,a
	ld	b,0
	ld	hl,dac_status
	add	hl,bc
	ld	a,(hl)
	cp	255
	jr	nz,_timer_dac_off
	xor	a
	jr	_timer_dac_mix
_timer_dac_off:
	srl	a
_timer_dac_mix:
	ld	(led_data),a
	xor	a
	ld	(timer),a
	led_set
	led_out
	ld	a,(led_phase+1)
	inc	a
	ld	(led_phase+1),a
	bit	5,a
	ret	z
	ld	a,00000001b
	ld	(led_phase+0),a
	xor	a
	ld	(led_phase+1),a
	ret

;##### A/D Subroutunes #####
ad_convert:
	call	timer_check
	ld	hl,ad_status
	ld	a,(ad_no)
	ld	c,a
	ld	b,0
	add	hl,bc
	ld	a,(hl)
	cp	0
	jr	nz,_ad_conv
	ld	a,(ad_no)
	inc	a
	and	00011111b
	ld	(ad_no),a
	ret
_ad_conv:
	cp	2
	jp	z,_ad_check
_ad_new:
	cp	1
	jr	z,_ad_new_go
	xor	a
	ld	(hl),a
	ret
_ad_new_go:
	ld	a,2
	ld	(hl),a
	ld	a,(ad_no)
	and	00000111b
	ld	(ad_comm),a
	ld	a,(ad_no)
	and	00011000b
	cp	00000000b
	jp	z,_ad_0
	cp	00001000b
	jp	z,_ad_1
	cp	00010000b
	jp	z,_ad_2
	jp	_ad_3
_ad_0:
	ld	a,(ad_comm)
	pb_set	0
	ld	a,(ad_comm)
	or	00001000b
	pb_set	0
	ld	a,(ad_comm)
	and	11110111b
	pb_set	0
	ld	a,00000001b
	ld	(eoc_mask),a
	ret
_ad_1:
	ld	a,(ad_comm)
	pb_set	1
	ld	a,(ad_comm)
	or	00001000b
	pb_set	1
	ld	a,(ad_comm)
	and	11110111b
	pb_set	1
	ld	a,00000010b
	ld	(eoc_mask),a
	ret
_ad_2:
	ld	a,(ad_comm)
	pb_set	2
	ld	a,(ad_comm)
	or	00001000b
	pb_set	2
	ld	a,(ad_comm)
	and	11110111b
	pb_set	2
	ld	a,00000100b
	ld	(eoc_mask),a
	ret
_ad_3:
	ld	a,(ad_comm)
	pb_set	3
	ld	a,(ad_comm)
	or	00001000b
	pb_set	3
	ld	a,(ad_comm)
	and	11110111b
	pb_set	3
	ld	a,00001000b
	ld	(eoc_mask),a
	ret
_ad_check:
	ld	a,(sel_4051)
	and	01111111b
	pb_set	7
	in	a,(pio_a)
	and	00001111b
	ld	b,a
	ld	a,(sel_4051)
	pb_set	7
	ld	a,(eoc_mask)
	and	b
	ret	z
	ld	a,(ad_no)
	and	00011000b
	cp	00000000b
	jp	z,_ad_d_0
	cp	00001000b
	jp	z,_ad_d_1
	cp	00010000b
	jp	z,_ad_d_2
	jp	_ad_d_3
_ad_d_0:
	ld	a,00010000b
	pb_set	0
	in	a,(pio_a)
	ld	d,a
	xor	a
	pb_set	0
	jp	_ad_trsnsmit
_ad_d_1:
	ld	a,00010000b
	pb_set	1
	in	a,(pio_a)
	ld	d,a
	xor	a
	pb_set	1
	jp	_ad_trsnsmit
_ad_d_2:
	ld	a,00010000b
	pb_set	2
	in	a,(pio_a)
	ld	d,a
	xor	a
	pb_set	2
	jp	_ad_trsnsmit
_ad_d_3:
	ld	a,00010000b
	pb_set	3
	in	a,(pio_a)
	ld	d,a
	xor	a
	pb_set	3
_ad_trsnsmit:
	ld	hl,ad_status
	ld	a,(ad_no)
	ld	c,a
	ld	b,0
	add	hl,bc
	ld	a,1
	ld	(hl),a
	ld	hl,ad_old
	ld	a,(ad_no)
	ld	c,a
	ld	b,0
	add	hl,bc
	srl	d			; [d] = new 7bit data
	ld	a,d
	ld	b,(hl)			; [b] = old
	cp	b			; a - b ?
	jr	c,_ad_inv		; a < b
	sub	b
_ad_cmp:
	ld	b,a
	ld	a,(threshold)
	cp	b			; (a-b)<thrshold ?
	jp	nc,_ad_out		; then NOP
	ld	(hl),d			; new [old] data set
	jr	_ad_event
_ad_inv:
	ld	c,a
	ld	a,b
	sub	c
	jr	_ad_cmp
_ad_event:
	ld	c,d
	ld	a,(outstatus)
	ld	b,a
	call	tx_fifo_set
	ld	a,(ad_no)
	ld	b,a
	call	tx_fifo_set
	ld	b,c
	call	tx_fifo_set
	ld	a,00000111b
	ld	(led_mode),a
	ld	a,(ad_no)
	ld	(led_ch),a
	ld	a,c
	ld	(led_data),a
	xor	a
	ld	(timer),a
	led_set
	led_out
_ad_out:
	ld	a,(ad_no)
	inc	a
	and	00011111b
	ld	(ad_no),a
	ret

;##### D/A Subroutines #####
dac_trans:
	latch_7
	ld	a,(dac_no)
	inc	a
	and	00011111b
	ld	(dac_no),a
	ld	c,a
	ld	hl,dac_status
	ld	b,0
	add	hl,bc
	ld	a,(hl)
	cp	255			; D/A on ?
	jr	nz,_dac_set
	ret
dac_off:
	latch_7
	ld	hl,dac_status
	ld	a,b			; off channel = [B]
	ld	(dac_no),a
	ld	c,a
	ld	b,0
	add	hl,bc
	ld	a,255			; off = 255
	ld	(hl),a
	xor	a
_dac_set:
	dac_out				; input = [A}
	ld	a,(dac_no)
	or	11111000b
	ld	(sel_4051),a
	ld	a,(dac_no)
	and	00011000b
	cp	00000000b
	jr	z,_dac_off_00
	cp	00001000b
	jr	z,_dac_off_01
	cp	00010000b
	jr	z,_dac_off_10
	jr	_dac_off_11
_dac_off_00:
	ld	a,(sel_4051)
	and	11110111b
	jr	_dac_off_exit
_dac_off_01:
	ld	a,(sel_4051)
	and	11101111b
	jr	_dac_off_exit
_dac_off_10:
	ld	a,(sel_4051)
	and	11011111b
	jr	_dac_off_exit
_dac_off_11:
	ld	a,(sel_4051)
	and	10111111b
_dac_off_exit:
	pb_set	7
	ret

;##### MIDI Subroutines #####
tx_data_check:
	ld	de,(tx_end)
	ld	hl,(tx_top)
	and	a			; CY <-- 0
	sbc	hl,de
	ret	z
	io_set	sio_a,00000000b		; Resister Point = 0
	in	a,(sio_a+1)
	bit	2,a
	ret	z
	ld	a,10001000b
	or	d
	ld	h,a
	ld	l,e
	ld	a,(hl)
	out	(sio_a),a
	inc	de
	res	3,d
	ld	(tx_end),de
	ret
tx_fifo_set:
	ld	de,(tx_top)
	ld	a,10001000b
	or	d
	ld	h,a
	ld	l,e
	ld	(hl),b
	inc	de
	res	3,d
	ld	(tx_top),de
	ret
rx_data_check:
	ld	de,(rx_end)
	ld	hl,(rx_top)
	and	a			; CY <-- 0
	sbc	hl,de
	ret	z
	ld	a,10000000b
	or	d
	ld	h,a
	ld	l,e
	ld	b,(hl)
	inc	de
	res	3,d
	ld	(rx_end),de
	bit	7,b
	jr	z,50$			; running
	ld	a,b
	cp	0f8h
	ret	nc
	cp	0f0h
	jr	c,10$
	xor	a
	ld	(rsb),a
	ret
10$:
	ld	a,b
	and	00001111b
	ld	(channel),a
	ld	a,b
	and	11110000b
	ld	(rsb),a
	xor	a
	ld	(dcb),a
	ret
50$:
	ld	a,(rsb)
	cp	0
	ret	z
	cp	0c0h
	ret	z
	cp	0d0h
	ret	z
	ld	a,(dcb)
	cp	0
	jr	nz,90$
	inc	a
	ld	(dcb),a
	ld	a,b
	ld	(keyno),a
	ret
90$:
	xor	a
	ld	(dcb),a
	ld	c,b			; 3rd Data
	ld	a,(rsb)
	ld	b,a
	ld	a,(channel)
	or	b
	cp	0afh
	ret	nz
	ld	a,(keyno)
	and	11110000b
	cp	00110000b
	jp	z,_af_30_4f
	cp	01000000b
	jp	z,_af_30_4f
	ld	a,(keyno)
	and	11100000b
	jp	z,_af_00_1f
	ld	a,(keyno)
	cp	20h
	jp	z,_af_20
	cp	21h
	jp	z,_af_21
	cp	22h
	jp	z,_af_22
	ret
_af_00_1f:
	ld	a,c
	cp	0
	jr	z,_af_00_ok
	cp	1
	jr	z,_af_00_ok
	ret
_af_00_ok:
	ld	hl,ad_status
	ld	a,(keyno)
	ld	e,a
	ld	d,0
	add	hl,de
	ld	(hl),c
	ld	a,00000001b
	ld	(led_mode),a
	ld	(led_phase+0),a
	ld	a,(keyno)
	ld	(led_ch),a
	ld	(led_phase+1),a
	ld	a,c
	ld	(led_data),a
	xor	a
	ld	(timer),a
	led_set
	led_out
	ret
_af_20:
	ld	a,c
	and	11110000b
	ret	nz
	ld	a,(outstatus)
	and	11110000b
	or	c
	ld	(outstatus),a
_led_disp:
	ld	a,00000010b
	ld	(led_mode),a
	ld	(led_phase+0),a
	ld	a,00000001b
	ld	(led_ch),a
	ld	(led_phase+1),a
	ld	a,(outstatus)
	ld	(led_data),a
	xor	a
	ld	(timer),a
	led_set
	led_out
	ret
_af_21:
	ld	a,c
	cp	08h
	jr	nz,_21_not_8
	ld	b,080h
	jp	_21_mix
_21_not_8:
	cp	09h
	jr	nz,_21_not_9
	ld	b,090h
	jp	_21_mix
_21_not_9:
	cp	0ah
	jr	nz,_21_not_a
	ld	b,0a0h
	jp	_21_mix
_21_not_a:
	cp	0bh
	jr	nz,_21_not_b
	ld	b,0b0h
	jp	_21_mix
_21_not_b:
	cp	0eh
	jr	nz,_21_not_e
	ld	b,0e0h
	jp	_21_mix
_21_not_e:
	ret
_21_mix:
	ld	a,(outstatus)
	and	00001111b
	or	b
	ld	(outstatus),a
	jp	_led_disp
_af_22:
	ld	a,c
	ld	(threshold),a
	ld	a,00000010b
	ld	(led_mode),a
	ld	(led_phase+0),a
	ld	a,00010000b
	ld	(led_ch),a
	ld	(led_phase+1),a
	ld	a,c
	ld	(led_data),a
	xor	a
	ld	(timer),a
	led_set
	led_out
	ret
_af_30_4f:
	ld	a,(keyno)
	sub	30h
	ld	e,a
	ld	hl,dac_status
	ld	d,0
	add	hl,de
	ld	b,c
	sla	c
	ld	(hl),c
	ld	a,00000100b
	ld	(led_mode),a
	ld	(led_phase+0),a
	ld	a,e
	ld	(led_ch),a
	ld	(led_phase+1),a
	ld	a,b
	ld	(led_data),a
	xor	a
	ld	(timer),a
	led_set
	led_out
	ret

	end

============================================================================