;-------------------------------------------------
;
;	MIDI delay measurement test : Sep. 1998
;
;		PA-2 : Event Trigger SW (active-low)
;		PA-3 : Mode SW ( 0:single, 1:heavy-traffic )
;		PB-0 : Transmit Signal output
;
;-------------------------------------------------

;##### Port Defines #####
smr	.equ	h'0fffb0
brr	.equ	h'0fffb1
scr	.equ	h'0fffb2
tdr	.equ	h'0fffb3
ssr	.equ	h'0fffb4
rdr	.equ	h'0fffb5
paddr	.equ	h'0fffd1
padr	.equ	h'0fffd3
pbddr	.equ	h'0fffd4
pbdr	.equ	h'0fffd6
iprb	.equ	h'0ffff8

;##### Vector Defines #####
	.section vector,data,locate=h'000000
	.data.l	start
	.org	h'0000d0

;##### Work RAM Data Defines #####
	.section ram,data,locate=h'0fef10
tx_top	.res.w	1
tx_end	.res.w	1
timer1	.res.w	1
timer2	.res.w	1
counter	.res.b	1
sw_old	.res.b	1
	.org	h'0ff800
tx_fifo	.res.b	1024

;***** Reset --> Initialize --> Main Loop *****
	.section program,code,locate=h'000100
start:
	mov.l	#h'0fff0f,er7		; stack pointer set
	mov.l	#h'0fef10,er2
	mov.w	#h'0fe0,r1
	mov.b	#0,r0l
_ram_clear:
	mov.b	r0l,@er2
	inc.l	#1,er2
	dec.w	#1,r1
	bne	_ram_clear
	jsr	@sci0_init		; SCI initialize
	mov.b	#b'00000000,r0l
	mov.b	r0l,@paddr		; set : Port[A] all input
	mov.b	#b'11111111,r0l
	mov.b	r0l,@pbddr		; set : Port[B] all output
	jsr	@wait_500msec
	mov.b	#b'01110000,r0l		; tx/rx start !
	mov.b	r0l,@scr
	mov.b	#b'11111111,r0l
	mov.b	r0l,@sw_old
	mov.b	#b'00000000,r0l
	mov.b	r0l,@pbdr		; write to Port[B]
loop:
	jsr	@timer_check
	jsr	@tx_midi_check
	jmp	@loop

;***** SCI init / MIDI Transmit Routines *****
sci0_init:
	mov.b	#b'00000000,r0l
	mov.b	r0l,@scr
	mov.b	#b'00000000,r0l
	mov.b	r0l,@smr
	mov.b	#15,r0l
	mov.b	r0l,@brr
	mov.w	#500,r0
_sci0_wait:
	dec.w	#1,r0
	bne	_sci0_wait
	mov.b	@ssr,r0l		; (dummy read)
	mov.b	#0,r0l
	mov.b	r0l,@ssr
	mov.b	#b'00001000,r0l
	mov.b	r0l,@iprb		; SCI0-int priority UP !
	rts
tx_midi_check:
	mov.w	@tx_top,r1
	mov.w	@tx_end,r6
	cmp.w	r1,r6
	bne	_tx_exist
	rts
_tx_exist:
	btst	#7,@ssr			; test TRDE
	bne	_tx_seq
	rts
_tx_seq:
	mov.w	#0,e6
	mov.b	@(tx_fifo,er6),r0l
	cmp.b	#h'ff,r0l
	beq	_tx_pass
	mov.b	r0l,@tdr
	bclr	#7,@ssr			; Transmit !
	jmp	@_tx_next
_tx_pass:
	mov.b	#b'11111111,r0l
	mov.b	r0l,@pbdr		; write to Port[B]
_tx_next:
	inc.w	#1,r6
	bclr	#2,r6h
	mov.w	r6,@tx_end
	rts
tx_fifo_set:
	mov.w	@tx_top,r6
	mov.w	#0,e6
	mov.b	r0h,@(tx_fifo,er6)	; transmit data = [r0h]
	inc.w	#1,r6
	bclr	#2,r6h
	mov.w	r6,@tx_top
	rts

;***** Timer / Counter Routines *****
wait_500msec:
	mov.l	#500,er1
_wait_1:
	jsr	@wait_1msec
	sub.l	#1,er1
	bne	_wait_1
	rts
wait_1msec:
	mov.l	#2048,er2
_wait_2:
	sub.l	#1,er2
	bne	_wait_2
	rts
timer_check:
	mov.w	@timer1,r1
	inc.w	#1,r1
	mov.w	r1,@timer1
	cmp.w	#700,r1
	beq	_timer_0
	rts
_timer_0:
	mov.w	#0,r1
	mov.w	r1,@timer1
_timer_1:
	jsr	@trigger
	mov.w	@timer2,r1
	inc.w	#1,r1
	mov.w	r1,@timer2
	cmp.w	#500,r1		; traffic density
	bne	_timer_2
	mov.w	#0,r1
	mov.w	r1,@timer2
_timer_2:
	mov.b	@padr,r0l		; new --> R0L
	btst	#3,r0l
	beq	_traffic
	rts
_traffic:
	mov.b	@counter,r0l
	inc.b	r0l
	bclr	#7,r0l
	mov.b	r0l,@counter
	mov.b	#h'90,r0h		; MIDI 1ch
	jsr	@tx_fifo_set
	mov.b	@counter,r0h
	jsr	@tx_fifo_set
	mov.b	#1,r0h			; min velocity
	jsr	@tx_fifo_set
	mov.b	@counter,r0h
	jsr	@tx_fifo_set
	mov.b	#0,r0h
	jsr	@tx_fifo_set
	mov.b	#h'9f,r0h		; MIDI 16ch
	jsr	@tx_fifo_set
	mov.b	@counter,r0h
	jsr	@tx_fifo_set
	mov.b	#1,r0h			; min velocity
	jsr	@tx_fifo_set
	mov.b	@counter,r0h
	jsr	@tx_fifo_set
	mov.b	#0,r0h
	jsr	@tx_fifo_set
	rts
trigger:
	mov.b	#b'00000000,r0l
	mov.b	r0l,@pbdr		; write to Port[B]
	mov.b	@padr,r0l		; new --> R0L
	mov.b	@sw_old,r0h		; old --> R0H
	mov.b	r0l,@sw_old
	btst	#2,r0l
	beq	_tr_1			; new SW = ON (low) !
	rts
_tr_1:
	btst	#2,r0h
	bne	_tr_2			; old SW = OFF (high) !
	rts
_tr_2:
	mov.b	#h'98,r0h		; MIDI 9 ch
	jsr	@tx_fifo_set
	mov.b	#84,r0h			; note 84
	jsr	@tx_fifo_set
	mov.b	#127,r0h		; max velocity
	jsr	@tx_fifo_set
	mov.b	#84,r0h
	jsr	@tx_fifo_set
	mov.b	#0,r0h
	jsr	@tx_fifo_set
	mov.b	#h'ff,r0h		; dummy data for trigger output
	jsr	@tx_fifo_set
	rts

	.end